TMS320C6678: Processor is generating more heat even in idle condition

Mani,

We first need to understand what is expected.  Please provide your completed C6678_Power_Consumption_Summary spreadsheet so that we know the amount of heat that must be dissipated for each chip.

Also, please confirm that you are using a Smart Reflex compliant power supply solution for each DSP.  Please provide the operating voltage measured on CVDD for each of the 3 DSPs.  Along with this, please provide the Voltage Control Identification Register (VCNTLID) value for each DSP (at 0x02350014).

Please provide details about your thermal environment.  What is the ambient temperature?  Is there any forced airflow over the heatsink?  How is the heatsink attached to the lids of the DSPs?  What is the ThetaCA for this heatsink under these conditions?  What is the thermal rating for the material under the heatsink?

Tom

Dear Sir,

We are using the Smart Reflex compliant power supply solution for each DSP. Reference is taken from K2E EVM Schematics. 

TPS544C25RVFT and LM10011SD/NOPB is used for CVDD Generation. I have enclosed my schematics (CVDD generation for DSP-1) and in similar way CVDD is generated for other 2 DSPs.

Voltage Control Identification Register (VCNTLID) value for each DSP (at 0x02350014)

DSP-1:  0F790000

DSP-2:  0F7D0000

DSP-S:  0FFF0000

Measured CVDD Voltage for each DSPs are below

DSP-1 : 0.975V

DSP-2 :  0.995V

DSP-S : 1.006V

1780.C6678_Power_Consumption_Summary_Rev3_4.xls

Thermal Environment details

We are putting this board with full heatsink in conduction cooled chassis.

What is the ambient temperature?

Ambient temperature around the chassis in 30 degree C.

Is there any forced airflow over the heatsink?

No. Forced airflow setup is not used over heatsink as it is conduction Cooled design.

How is the heatsink attached to the lids of the DSPs?

Thermal Pad (P/N EYG-TE0E0A20A) is used between IC and Heatsink.

What is the thermal rating for the material under the heatsink?

-40 to 150 degree C

1780.C6678_Power_Consumption_Summary_Rev3_4.xls

What is the ThetaCA for this heatsink under these conditions.?

5W/m² K 

CVDD Section.pdf

Regards,

Mani.

 Mani,

This is not the source of your heat issue, but the CVDD voltages are all about 8.5% low, which is outside of the spec. This needs to be resolved. After initial power-up and before reset is released, the power supply measured at the DSP needs to have a nominal output voltage of 1.1V +/-5%.

Your utilization rates for CorePac 0 are unrealistically high and the utilization rate for many of the peripherals is also unrealistically high. Please read through the referenced User Guide at: http://www.ti.com/lit/pdf/SPRABI5. Remember that each C66x DSP core has 8 parallel execution units. 100% utilization means that it is completing 8 execution steps on every clock cycle. Realistically, even with highly optimized assembly code fully in the instruction cache and all data stored in local L1 or L2 memory, you can only sustain 2-3 execution steps per clock. As soon as there is a cache miss or when more data needs to be pulled from external memory, the processor stalls. That is why we recommend that you set the SP% no higher than 27% - this would equate to execution of the best case scenario described above. If you want to add a percentage for CC%, the SP% needs to go down. This could be modeled in a simulator but that requires significant effort. Otherwise, for your worst-case power consumption, we recommend that you use 27% SP and 0% CC. That being said, since the other 7 CorePacs are lightly loaded, your overall chip power consumption is within a reasonable range. Since power dissipated is roughly equal to power consumed, you will need to dissipate 11W of heat.

You indicate that the ambient temperature around the chassis is 30C. Is this the maximum ambient temperature? This conduction cooled chassis must dissipate the heat from all 3 DSPs as well as memories, power supply conversion ICs and all of the other parts on the board that consume power. You will need to perform 3D thermal modeling for this design to get an accurate answer. However, using simple thermal resistances, you should get an approximate understanding of your thermal model.

Please refer to the Thermal Design Guide for DSP and ARM Application Processors Application Report SPRABI3B. Figure 3 provides an understanding of this challenge. The C6678 Data Manual on page 241 states that the thermal resistance (Theta-JC) from the junction to the case is 0.18C/W. (This would be the same as Degrees (K)/Watt.) You mentioned a TIM material. What is its thermal resistance in its installed thickness? Lastly, in the worst-case environment, what is the thermal resistance from the conduction enclosure to the ambient environment, Theta-CA? These thermal resistances are in series and they add. By multiplying this sum times the dissipated power, you will get the expected temp rise of the junction over the ambient temperature. This is equation (1) in SPRABI3B.  There are sample calculations at the end of this document showing how this is used.

Tom

Hi Sir,

We have followed K2E reference schematic. Which is attached for your reference. In which, Do we need to tune anything to resolve the shortage of CVDD voltage (8.5%) from nominal CVDD voltage range?

K2E_EVM_SCH_16_00175_03-1.pdf

Regards,

Mani Selavm P

Mani,

As shown in the K2E schematic, the VSET resistor needs to be 121K to set an initial voltage of 1.10V.  Your schematic incorrectly states that 51.5K is needed for 1.00V.  The default output from the supply need to be 1.1V, nominal, prior to being reduced when the VID code is latched.

Tom

Hi Tom,

Sorry for delayed response.

With your input, our MECHANICAL team is  modifying heat sink design to dissipate the heat effectively with our vendor. As COVID-19 lockdown, work is going very slow in our vendor side.

Time being we can close this thread temporarily. 

I will come back to you after new heat sink design and manufacturing is done with reference of this thread.

Thank you so much for your great support.

Regards,

Mani Selvam P