mcBSP Digital Loopback in OMAPL138

ranchu

Guru 20755 points

Other Parts Discussed in Thread: OMAP3530, OMAPL138

Hello,

I have configured the mcBSP0 to digital loopback, but every write to the BFIFO data (0x1f10000), I see that the RFIFO STATUS register contains in RLVL 2 more messeges then before the write. for example if I do:

mw 0x1f10000 xxx 1 (xxx=any value)
and then: md 0x1d10014 1, I will see that it is larger in 2 then from last time (instead of 1 as I expected). When I read from the fifo, I see that the count of the RFIFO is smaller in 1, as I expected.
I would like to know why is it that the in the writing, count of RFIFO RLVL is bigger in 2 (and not 1) then before the writing.

The configuration: 1 X/R frame word, 32 bits word length, fper =32, fwid=16, numdma=1, numevent =0, delay=1bit.

Any Ideas are welcomed.

Regards,

Ran

over 14 years ago

0 Sugumar Natarajan over 14 years ago

Intellectual 670 points

Hi ran,

Are you saying that the single write to BFIFO increment the RFIFO STATUS RLVL by 2 instead of 1 and read from RFIFO decrements the RFIFO STATUS RLVL by 1?. Can you post more information on how you are testing?. I mean how are the registers configured (uboot using md/ kernel) , configuration sequence and the data transfer mode?

Moreover, what is the value of the WFIFO RLVL status after write?

Regards,

N.Sugumar

0 ranchu over 14 years ago in reply to Sugumar Natarajan

Guru 20755 points

Hi Sugumar,

Yes, that is right: in the digital loopback, a single write to BFIFO increment the RFIFO STATUS RLVL by 2 instead of 1 and read from RFIFO decrements the RFIFO STATUS RLVL by 1.
the registers are configured in the uboot. I based my loopback program on an example posted in the forum for the OMAP3530 https://e2e.ti.com/support/dsp/omap_applications_processors/f/447/t/52300.aspx?PageIndex=2 . I made changes for it to fit to the OMAPL138 (instead OMAP3530 ).

I configured to use CLKI (instead of CLKS in the original loopback example).

I use: frame phase =1 , 1 X/R frame word, 32 bits word length, fper =32, fwid=16, numdma=1, numevent =0, delay=1bit , using CLKI , freq = 7. configuration sequence is as done in the original loopback example, [ the BFIFO is added so that first I initialize the numevent, numdma, later enable the BFIFO, and only then remove reset of transmitter and reciever. and then it is checked with mw, md commands from the u-boot shell.

I can add the relevant files if needed,

Best Regards,

Ran

0 ranchu over 14 years ago in reply to Sugumar Natarajan

Guru 20755 points

Hello Sugumar Natarajan,

In addition to my previous reply, here is the code I use.

Thank you very much for the assistance,

Ran.

*
* McBSP initializations
*
* ranran
*/

#include "mcbsp.h"
#include "operations.h"
#include "mcbsp_lib.h"

#define MY_MCBSP      MCBSP1
#define SRG_FPER      32     // procedure subtracts 1
#define SRG_FWID      16    // procedure subtracts 1
#define SRG_CLKDV     7
#define FRAME1_WORDS 1
#define FRAME2_WORDS 1   // Dual phase only
#define BFIFO_ENABLED 1
#define WNUMDMA       1
#define WNUMEVT       0
#define RNUMDMA       1
#define RNUMEVT       0

int mcbsp_init (void)
{

/////////////////////////////////////////////////////////////
// reset module
mcbspReset(MY_MCBSP, 1);

/////////////////////////////////////////////////////////////
// Configure transmitter and receiver
mcbspSetRxMode(MY_MCBSP, CLK_EXTERNAL, CLKR_SAMPLE_FALL, SYNC_EXTERNAL, SYNC_ACTIVE_HIGH, FULL_CYCLE);
mcbspSetTxMode(MY_MCBSP, CLK_INTERNAL, CLKX_DRIVE_RISE, SYNC_INTERNAL, SYNC_ACTIVE_HIGH, HALF_CYCLE, DXENA_OFF, XCLK_FREE, FSX_GATED);

/////////////////////////////////////////////////////////////
// Set up frames
mcbspRxFrameSetup(MY_MCBSP, SINGLE_PHASE, MSB_FIRST, DELAY_1BIT, FRAME1_WORDS, WORD_32BITS, FRAME2_WORDS, WORD_32BITS, RIGHT_JUST_ZERO);
mcbspTxFrameSetup(MY_MCBSP, SINGLE_PHASE, MSB_FIRST, DELAY_1BIT, FRAME1_WORDS, WORD_32BITS, FRAME2_WORDS, WORD_32BITS);

/////////////////////////////////////////////////////////////
// Program the Sample Rate generator
mcbspSetupSrg(MY_MCBSP, CLKI/*ranran TODO !!! CLKS*/, CLKS_RISE, SRG_FREE, SRG_FPER , SRG_FWID, SRG_CLKDV);

/////////////////////////////////////////////////////////////
// Configure BFIFO
if (BFIFO_ENABLED)
{
    mcbspSetWFIFO(MY_MCBSP,WNUMDMA, WNUMEVT);
    mcbspSetRFIFO(MY_MCBSP,RNUMDMA, RNUMEVT);
}

/////////////////////////////////////////////////////////////
// Delay to allow settings to sync
//
udelay(100);

if (BFIFO_ENABLED)
{
    mcbspEnableWFIFO(MY_MCBSP);
    mcbspEnableRFIFO(MY_MCBSP);
}
mcbspLoopback(MY_MCBSP, DIGITAL_LOOPBACK);
udelay(100);
/////////////////////////////////////////////////////////////
// Remove Resets

mcbspRemoveResetSrg(MY_MCBSP);
mcbspRemoveResetFsg(MY_MCBSP);
mcbspRemoveResetRx(MY_MCBSP);
mcbspRemoveResetTx(MY_MCBSP);

/* ranran put in remarks
OUT_REGL(MY_MCBSP + MCBSPLP_IRQSTATUS_REG, 0x0); // Clear IRQ bits
*/

return 0;
}

---------------------------------------------------------------------

/* McBSP Function Library Source File
*
* ranran
*/

#include "mcbsp.h"
#include "operations.h"
#include "mcbsp_lib.h"

/////////////////////////////////////////////////////////////
// Enable the functional clock for the McBSP module
//
void mcbspReset(unsigned int ulModule, unsigned char ulBlock)
{
mcbspResetRx(ulModule);
mcbspResetTx(ulModule);
mcbspResetFsg(ulModule);
mcbspResetSrg(ulModule);
if (ulBlock)
{
while(CHKBIT_REGL(ulModule + MCBSPLP_SPCR_REG, SPCR_GRST)); // Wait until GRST bit is clear
}
}

/////////////////////////////////////////////////////////////
// Setup the tranmsitter
//
void mcbspSetTxMode(unsigned int ulModule,
                    unsigned char ulCLKXM,
                    unsigned char ulCLKXP,
                    unsigned char ulFSXM,
                    unsigned char ulFSXP,
                    unsigned char ulCYCLE,
                    unsigned char ulDXENAMode,
                    unsigned char ulEXTCLKGATE,
                    unsigned char ulFSGM)
{

CLRBIT_REGL(ulModule + MCBSPLP_PCR_REG, PCR_FSXM + PCR_CLKXM + PCR_FSXP + PCR_CLKXP); // clear the appropriate bits
SETBIT_REGL(ulModule + MCBSPLP_PCR_REG, (ulFSXM<<11) + (ulCLKXM<<9) + (ulFSXP<<3) + (ulCLKXP<<1));
CLRBIT_REGL(ulModule + MCBSPLP_SRGR_REG, SRGR_FSGM);
SETBIT_REGL(ulModule + MCBSPLP_SRGR_REG, (ulFSGM<<12));

switch (ulDXENAMode)
{
case (DXENA_OFF):
   CLRBIT_REGL(ulModule + MCBSPLP_SPCR_REG, SPCR_DXENA);
   break;
case (DXENA_DLY1):
   SETBIT_REGL(ulModule + MCBSPLP_SPCR_REG, SPCR_DXENA);
   break;
case (DXENA_DLY2):
   SETBIT_REGL(ulModule + MCBSPLP_SPCR_REG, SPCR_DXENA);
   break;
case (DXENA_DLY3):
   SETBIT_REGL(ulModule + MCBSPLP_SPCR_REG, SPCR_DXENA);
   break;
case (DXENA_DLY4):
   SETBIT_REGL(ulModule + MCBSPLP_SPCR_REG, SPCR_DXENA);
   break;
default:
   break;
}
/*
CLRBIT_REGL(ulModule + MCBSPLP_XCCR_REG, XCCR_XFULL_CYCLE + XCCR_EXTCLKGATE);
SETBIT_REGL(ulModule + MCBSPLP_XCCR_REG, (ulCYCLE<<11) + (ulEXTCLKGATE<<15)); ranran */

}

/////////////////////////////////////////////////////////////
// Setup the receiver
//

void mcbspSetRxMode(unsigned int ulModule,
                    unsigned char ulCLKRM,
                    unsigned char ulCLKRP,
                    unsigned char ulFSRM,
                    unsigned char ulFSRP,
                    unsigned char ulCYCLE)
{

CLRBIT_REGL(ulModule + MCBSPLP_PCR_REG, PCR_FSRM + PCR_CLKRM + PCR_FSRP + PCR_CLKRP); // clear the appropriate bits
SETBIT_REGL(ulModule + MCBSPLP_PCR_REG, (ulFSRM<<11) + (ulCLKRM<<9) + (ulFSRP<<3) + (ulCLKRP<<1));
/*if (ulCYCLE)
{
    SETBIT_REGL(ulModule + MCBSPLP_RCCR_REG, RCCR_RFULL_CYCLE);
} else {
    CLRBIT_REGL(ulModule + MCBSPLP_RCCR_REG, RCCR_RFULL_CYCLE);
} ranran */
}

/////////////////////////////////////////////////////////////
// Setup the receive frame
//
void mcbspRxFrameSetup(unsigned int ulModule,
                       unsigned char ulRPHASE,
                       unsigned char ulRREVERSE,
                       unsigned char ulRDATDLY,
                       unsigned char ulRFRLEN1,
                       unsigned char ulRWDLEN1,
                       unsigned char ulRFRLEN2,
                       unsigned char ulRWDLEN2,
                       unsigned char ulRJUST)

{
OUT_REGL(ulModule + MCBSPLP_RCR_REG, ((ulRFRLEN1-1)<<8) + (ulRWDLEN1<<5));
OUT_REGL(ulModule + MCBSPLP_RCR_REG, (ulRPHASE<<15) + (ulRFRLEN2<<8) + (ulRWDLEN2<<5) + (ulRREVERSE<<3) + ulRDATDLY);
CLRBIT_REGL(ulModule + MCBSPLP_SPCR_REG, SPCR_RJUST_1 + SPCR_RJUST_0);
SETBIT_REGL(ulModule + MCBSPLP_SPCR_REG, (ulRJUST<<13));
}

/////////////////////////////////////////////////////////////
// Setup the receive frame
//
void mcbspTxFrameSetup(unsigned int ulModule,
                       unsigned char ulXPHASE,
                       unsigned char ulXREVERSE,
                       unsigned char ulXDATDLY,
                       unsigned char ulXFRLEN1,
                       unsigned char ulXWDLEN1,
                       unsigned char ulXFRLEN2,
                       unsigned char ulXWDLEN2)

{
OUT_REGL(ulModule + MCBSPLP_XCR_REG, ((ulXFRLEN1-1)<<8) + (ulXWDLEN1<<5));
OUT_REGL(ulModule + MCBSPLP_XCR_REG, (ulXPHASE<<15) + (ulXFRLEN2<<8) + (ulXWDLEN2<<5) + (ulXREVERSE<<3) + ulXDATDLY);
}

/////////////////////////////////////////////////////////////
// Select the clock source
//
void mcbspSetupSrg(unsigned int ulModule,
                   unsigned char ulSource,
                   unsigned char ulCLKSP,
                   unsigned char ulGSYNC,
                   unsigned char ulFPER,
                   unsigned char ulFWID,
                   unsigned char ulCLKGDV)
{
OUT_REGL(ulModule + MCBSPLP_SRGR_REG, ((ulFWID-1)<<8) + ulCLKGDV);
CLRBIT_REGL(ulModule + MCBSPLP_SRGR_REG, SRGR_GSYNC + SRGR_CLKSP + SRGR_FPER_MASK);
SETBIT_REGL(ulModule + MCBSPLP_SRGR_REG, (ulGSYNC<<15) + (ulCLKSP<<14) + (ulFPER-1));

switch(ulSource) {
  case(CLKS):
    CLRBIT_REGL(ulModule + MCBSPLP_PCR_REG, PCR_SCLKME);
    CLRBIT_REGL(ulModule + MCBSPLP_SRGR_REG, SRGR_CLKSM);
    break;
  case(CLKI):
    CLRBIT_REGL(ulModule + MCBSPLP_PCR_REG, PCR_SCLKME);
    SETBIT_REGL(ulModule + MCBSPLP_SRGR_REG, SRGR_CLKSM);
    break;
  case(CLKR):
    SETBIT_REGL(ulModule + MCBSPLP_PCR_REG, PCR_SCLKME);
    CLRBIT_REGL(ulModule + MCBSPLP_SRGR_REG, SRGR_CLKSM);
    break;
  case(CLKX):
    SETBIT_REGL(ulModule + MCBSPLP_PCR_REG, PCR_SCLKME);
    SETBIT_REGL(ulModule + MCBSPLP_SRGR_REG, SRGR_CLKSM);
    break;
  default:
    break;
}
}

/////////////////////////////////////////////////////////////
// Enable Sample Rate Generator
void mcbspRemoveResetSrg (unsigned int ulModule)
{
SETBIT_REGL(ulModule + MCBSPLP_SPCR_REG, SPCR_GRST);
}

/////////////////////////////////////////////////////////////
// Reset Sample Rate Generator
void mcbspResetSrg (unsigned int ulModule)
{
CLRBIT_REGL(ulModule + MCBSPLP_SPCR_REG, SPCR_GRST);
}

/////////////////////////////////////////////////////////////
// Enable Receiver
void mcbspRemoveResetRx (unsigned int ulModule)
{
SETBIT_REGL(ulModule + MCBSPLP_SPCR_REG, SPCR_RRST);
}

/////////////////////////////////////////////////////////////
// Reset Receiver
void mcbspResetRx(unsigned int ulModule)
{
CLRBIT_REGL(ulModule + MCBSPLP_SPCR_REG, SPCR_RRST);
}

/////////////////////////////////////////////////////////////
// Enable Transmtter
void mcbspRemoveResetTx (unsigned int ulModule)
{
SETBIT_REGL(ulModule + MCBSPLP_SPCR_REG, SPCR_XRST);
}

/////////////////////////////////////////////////////////////
// Reset Transmtter
void mcbspResetTx (unsigned int ulModule)
{
CLRBIT_REGL(ulModule + MCBSPLP_SPCR_REG, SPCR_XRST);
}

/////////////////////////////////////////////////////////////
// Enable Frame Sync generator
void mcbspRemoveResetFsg (unsigned int ulModule)
{
SETBIT_REGL(ulModule + MCBSPLP_SPCR_REG, SPCR_FRST);
}

/////////////////////////////////////////////////////////////
// Enable Frame Sync generator
void mcbspResetFsg (unsigned int ulModule)
{
CLRBIT_REGL(ulModule + MCBSPLP_SPCR_REG, SPCR_FRST);
}

/////////////////////////////////////////////////////////////
// Enable Receiver
void mcbspEnableRx (unsigned int ulModule)
{
CLRBIT_REGL(ulModule + MCBSPLP_SPCR_REG, SPCR_RRST);
}

/////////////////////////////////////////////////////////////
// Disable Receiver
void mcbspDisableRx (unsigned int ulModule)
{
SETBIT_REGL(ulModule + MCBSPLP_SPCR_REG, SPCR_RRST);
}

/////////////////////////////////////////////////////////////
// Set loopback mode
void mcbspLoopback(unsigned int ulModule, unsigned char ulMode)
{
switch(ulMode)
{
  case(NO_LOOPBACK):
    CLRBIT_REGL(ulModule + MCBSPLP_SPCR_REG, SPCR_ALB);
    break;
  case(DIGITAL_LOOPBACK):
    SETBIT_REGL(ulModule + MCBSPLP_SPCR_REG, SPCR_ALB);
    break;
  case(ANALOG_LOOPBACK):
  default:
    CLRBIT_REGL(ulModule + MCBSPLP_SPCR_REG, SPCR_ALB);
    break;

}
}

void mcbspDataPut(unsigned int ulModule, unsigned int ulData)
{
while (!CHKBIT_REGL(ulModule + MCBSPLP_SPCR_REG, SPCR_XRDY));
OUT_REGL(ulModule + MCBSPLP_DXR_REG, ulData);
}

void mcbspDataGet(unsigned int ulModule, unsigned int *pulData)
{
while(!CHKBIT_REGL(ulModule + MCBSPLP_SPCR_REG, SPCR_RRDY));
*pulData = IN_REGL(ulModule + MCBSPLP_DRR_REG);
}

unsigned char mcbspDataPutNoBlock(unsigned int ulModule, unsigned int ulData)
{
if(CHKBIT_REGL(ulModule + MCBSPLP_SPCR_REG, SPCR_XRDY))
{
OUT_REGL(ulModule + MCBSPLP_DXR_REG, ulData);
return 1;
} else {
return 0;
}
}

unsigned char mcbspDataGetNoBlock(unsigned int ulModule, unsigned int *pulData)
{
if(CHKBIT_REGL(ulModule + MCBSPLP_SPCR_REG, SPCR_RRDY))
{
*pulData = IN_REGL(ulModule + MCBSPLP_DRR_REG);
return 1;
} else {
return 0;
}
}

void mcbspEnableWFIFO(unsigned int ulModule)
{
SETBIT_REGL(ulModule + MCBS_WFIFO_CTR_REG, WENA);
}

void mcbspEnableRFIFO(unsigned int ulModule)
{
SETBIT_REGL(ulModule + MCBS_RFIFO_CTR_REG, RENA);
}

void mcbspSetWFIFO(unsigned int ulModule,unsigned char ulNumDma, unsigned char ulNumEvent)
{
OUT_REGL(ulModule + MCBS_WFIFO_CTR_REG, (ulNumDma)+(ulNumEvent<<8) );
}

void mcbspSetRFIFO(unsigned int ulModule,unsigned char ulNumDma, unsigned char ulNumEvent)
{
OUT_REGL(ulModule + MCBS_RFIFO_CTR_REG, (ulNumDma)+(ulNumEvent<<8) );
}

void mcbspDataPutFifo(unsigned int ulModule, unsigned int* pulData, int nLength)
{
unsigned int nCnt = 0;
do
{
      nCnt = IN_REGL(ulModule + MCBS_WFIFO_STS_REG);
      nCnt = nCnt & 0xff;
}
while(nCnt>0);

for(nCnt=0; nCnt<nLength; nCnt++)
{
    OUT_REGL(ulModule + MCBS_BFIFO_DATA_REG, pulData[nCnt]);
    udelay(100); /*TODO is it needed ?*/
}
}

void mcbspDataGetFifo(unsigned int ulModule, unsigned int *pulData, int nLength)
{
unsigned int nCnt = 0,nCnt2=0;
do
{
      nCnt = IN_REGL(ulModule + MCBS_RFIFO_STS_REG);
      nCnt = nCnt & 0xff;
}
while(nCnt<nLength);
   nCnt2 = IN_REGL(ulModule + MCBS_RFIFO_STS_REG);
   nCnt2 = nCnt2 & 0xff;

for(nCnt=0; nCnt<nLength; nCnt++)
{
    pulData[nCnt] = IN_REGL(ulModule + MCBS_BFIFO_DATA_REG);
    udelay(100); /*TODO is it needed ?*/
}
   nCnt = IN_REGL(ulModule + MCBS_RFIFO_STS_REG);
   nCnt = nCnt & 0xff;
}

----------------------------------------------------------------

ranran
*/

// Base addresses

#define MCBSP1_REG_BASE          0x01D10000
#define MCBSP2_REG_BASE          0x01D11000
#define MCBSP1_FIFO_CTRL_REG_BASE       0x01D10800
#define MCBSP2_FIFO_CTRL_REG_BASE       0x01D11800
#define MCBSP1_FIFO_DATA_REG_BASE       0x01F10000
#define MCBSP2_FIFO_DATA_REG_BASE       0x01F11000

// Module Offsets:

// MCBSP general
#define MCBSPLP_DRR_REG       (0x00000000)
#define MCBSPLP_DXR_REG       (0x00000004)
#define MCBSPLP_SPCR_REG      (0x00000008)
#define MCBSPLP_RCR_REG       (0x0000000C)
#define MCBSPLP_XCR_REG       (0x00000010)
#define MCBSPLP_SRGR_REG      (0x00000014)
#define MCBSPLP_MCR_REG       (0x00000018)
#define MCBSPLP_RCER0_REG     (0x0000001C)
#define MCBSPLP_XCER0_REG     (0x00000020)
#define MCBSPLP_PCR_REG       (0x00000024)
#define MCBSPLP_RCER1_REG     (0x00000028)
#define MCBSPLP_XCER1_REG     (0x0000002C)
#define MCBSPLP_RCER2_REG     (0x00000030)
#define MCBSPLP_XCER2_REG     (0x00000034)
#define MCBSPLP_RCER3_REG     (0x00000038)
#define MCBSPLP_XCER3_REG     (0x0000003C)

#define MCBS_WFIFO_CTR_REG    (0x00000810)
#define MCBS_WFIFO_STS_REG    (0x00000814)
#define MCBS_RFIFO_CTR_REG    (0x00000818)
#define MCBS_RFIFO_STS_REG    (0x0000081C)

// MCBSPLP_SPCR_REG
#define SPCR_FREE       (0x02000000)
#define SPCR_SOFT       (0x01000000)
#define SPCR_FRST       (0x00800000)
#define SPCR_GRST       (0x00400000)
#define SPCR_XINTM_1    (0x00200000)
#define SPCR_XINTM_0    (0x00100000)
#define SPCR_XSYNCERR   (0x00080000)
#define SPCR_XEMPTY     (0x00040000)
#define SPCR_XRDY       (0x00020000)
#define SPCR_XRST       (0x00010000)
//
#define SPCR_ALB        (0x00008000)
#define SPCR_RJUST_1    (0x00004000)
#define SPCR_RJUST_0    (0x00002000)
#define SPCR_CLKSTP_1   (0x00001000)
#define SPCR_CLKSTP_0   (0x00000800)
#define SPCR_DXENA      (0x00000080)
#define SPCR_RINTM_1    (0x00000020)
#define SPCR_RINTM_0    (0x00000010)
#define SPCR_RSYNCERR   (0x00000008)
#define SPCR_RFULL      (0x00000004)
#define SPCR_RRDY       (0x00000002)
#define SPCR_RRST       (0x00000001)

// MCBSPLP_RCR_REG
#define RCR_RPHASE (0x80000000)
#define RCR_RFRLEN2_6 (0x40000000)
#define RCR_RFRLEN2_5 (0x20000000)
#define RCR_RFRLEN2_4 (0x10000000)
#define RCR_RFRLEN2_3 (0x08000000)
#define RCR_RFRLEN2_2 (0x04000000)
#define RCR_RFRLEN2_1 (0x02000000)
#define RCR_RFRLEN2_0 (0x01000000)
#define RCR_RWDLEN2_2 (0x00800000)
#define RCR_RWDLEN2_1 (0x00400000)
#define RCR_RWDLEN2_0 (0x00200000)
#define RCR_RREVERSE_1 (0x00100000)
#define RCR_RREVERSE_0 (0x00080000)
#define RCR_RDATDLY_1 (0x00020000)
#define RCR_RDATDLY_0 (0x00010000)
//
#define RCR_RFRLEN1_6 (0x00004000)
#define RCR_RFRLEN1_5 (0x00002000)
#define RCR_RFRLEN1_4 (0x00001000)
#define RCR_RFRLEN1_3 (0x00000800)
#define RCR_RFRLEN1_2 (0x00000400)
#define RCR_RFRLEN1_1 (0x00000200)
#define RCR_RFRLEN1_0 (0x00000100)
#define RCR_RWDLEN1_2 (0x00000080)
#define RCR_RWDLEN1_1 (0x00000040)
#define RCR_RWDLEN1_0 (0x00000020)

// MCBSPLP_XCR_REG
#define XCR2_XPHASE (0x00008000)
#define XCR2_XFRLEN2_6 (0x00004000)
#define XCR2_XFRLEN2_5 (0x00002000)
#define XCR2_XFRLEN2_4 (0x00001000)
#define XCR2_XFRLEN2_3 (0x00000800)
#define XCR2_XFRLEN2_2 (0x00000400)
#define XCR2_XFRLEN2_1 (0x00000200)
#define XCR2_XFRLEN2_0 (0x00000100)
#define XCR2_XWDLEN2_2 (0x00000080)
#define XCR2_XWDLEN2_1 (0x00000040)
#define XCR2_XWDLEN2_0 (0x00000020)
#define XCR2_XREVERSE_1 (0x00000010)
#define XCR2_XREVERSE_0 (0x00000008)
#define XCR2_XDATDLY_1 (0x00000002)
#define XCR2_XDATDLY_0 (0x00000001)
//
#define XCR1_XFRLEN1_6 (0x00004000)
#define XCR1_XFRLEN1_5 (0x00002000)
#define XCR1_XFRLEN1_4 (0x00001000)
#define XCR1_XFRLEN1_3 (0x00000800)
#define XCR1_XFRLEN1_2 (0x00000400)
#define XCR1_XFRLEN1_1 (0x00000200)
#define XCR1_XFRLEN1_0 (0x00000100)
#define XCR1_XWDLEN1_2 (0x00000080)
#define XCR1_XWDLEN1_1 (0x00000040)
#define XCR1_XWDLEN1_0 (0x00000020)

// MCBSPLP_SRGR_REG
#define SRGR_GSYNC       (0x80000000)
#define SRGR_CLKSP       (0x40000000)
#define SRGR_CLKSM       (0x20000000)
#define SRGR_FSGM        (0x10000000)
#define SRGR_FPER_b      (0x08000000)
#define SRGR_FPER_a      (0x04000000)
#define SRGR_FPER_9      (0x02000000)
#define SRGR_FPER_8      (0x01000000)
#define SRGR_FPER_7      (0x00800000)
#define SRGR_FPER_6      (0x00400000)
#define SRGR_FPER_5      (0x00200000)
#define SRGR_FPER_4      (0x00100000)
#define SRGR_FPER_3      (0x00080000)
#define SRGR_FPER_2      (0x00040000)
#define SRGR_FPER_1      (0x00020000)
#define SRGR_FPER_0      (0x00010000)
#define SRGR_FPER_MASK   (0xFFF)
#define SRGR_FPER_BIT    (0)
//
#define SRGR_FWID_7      (0x00008000)
#define SRGR_FWID_6      (0x00004000)
#define SRGR_FWID_5      (0x00002000)
#define SRGR_FWID_4      (0x00001000)
#define SRGR_FWID_3      (0x00000800)
#define SRGR_FWID_2      (0x00000400)
#define SRGR_FWID_1      (0x00000200)
#define SRGR_FWID_0      (0x00000100)
#define SRGR_CLKGDV_7    (0x00000080)
#define SRGR_CLKGDV_6    (0x00000040)
#define SRGR_CLKGDV_5    (0x00000020)
#define SRGR_CLKGDV_4    (0x00000010)
#define SRGR_CLKGDV_3    (0x00000008)
#define SRGR_CLKGDV_2    (0x00000004)
#define SRGR_CLKGDV_1    (0x00000002)
#define SRGR_CLKGDV_0    (0x00000001)
#define SRGR_FWID_MASK   (0x0000FF00)
#define SRGR_CLKGDV_MASK (0x000000FF)
#define SRGR_FWID_BIT    (8)
#define SRGR_CLKGDV_BIT (0)

// MCBSPLP_MCR_REG
#define MCR_XMCME      (0x02000000)
#define MCR_XPBBLK_1   (0x01000000)
#define MCR_XPBBLK_0   (0x00800000)
#define MCR_XPABLK_1   (0x00400000)
#define MCR_XPABLK_0   (0x00200000)
#define MCR_XMCM_1     (0x00020000)
#define MCR_XMCM_0     (0x00010000)
//
#define MCR_RMCME      (0x00000200)
#define MCR_RPBBLK_1   (0x00000100)
#define MCR_RPBBLK_0   (0x00000080)
#define MCR_RPABLK_1   (0x00000040)
#define MCR_RPABLK_0   (0x00000020)
#define MCR_RMCM       (0x00000001)

// MCBSPLP_PCR_REG
#define PCR_IDLE_EN    (0x4000)
#define PCR_XIOEN      (0x2000)
#define PCR_RIOEN      (0x1000)
#define PCR_FSXM       (0x0800)
#define PCR_FSRM       (0x0400)
#define PCR_CLKXM      (0x0200)
#define PCR_CLKRM      (0x0100)
#define PCR_SCLKME     (0x0080)
#define PCR_CLKS_STAT (0x0040)
#define PCR_DX_STAT    (0x0020)
#define PCR_DR_STAT    (0x0010)
#define PCR_FSXP       (0x0008)
#define PCR_FSRP       (0x0004)
#define PCR_CLKXP      (0x0002)
#define PCR_CLKRP      (0x0001)

// MCBSP1
#define MCBSPLP_DRR_REG       (0x00000000)
#define MCBSPLP_DXR_REG       (0x00000004)
#define MCBSPLP_SPCR_REG      (0x00000008)
#define MCBSPLP_RCR_REG       (0x0000000C)
#define MCBSPLP_XCR_REG       (0x00000010)
#define MCBSPLP_SRGR_REG      (0x00000014)
#define MCBSPLP_MCR_REG       (0x00000018)
#define MCBSPLP_RCER0_REG     (0x0000001C)
#define MCBSPLP_XCER0_REG     (0x00000020)
#define MCBSPLP_PCR_REG       (0x00000024)
#define MCBSPLP_RCER1_REG     (0x00000028)
#define MCBSPLP_XCER1_REG     (0x0000002C)
#define MCBSPLP_RCER2_REG     (0x00000030)
#define MCBSPLP_XCER2_REG     (0x00000034)
#define MCBSPLP_RCER3_REG     (0x00000038)
#define MCBSPLP_XCER3_REG     (0x0000003C)

// MCBS_WFIFO_CTR_REG
#define WENA (0x000010000)
//MCBS_RFIFO_CTR_REG
#define RENA (0x000010000)

#define MCBS_REVISION_REG     (0x00000800)
#define MCBS_WFIFO_CTR_REG    (0x00000810)
#define MCBS_WFIFO_STS_REG    (0x00000814)
#define MCBS_RFIFO_CTR_REG    (0x00000818)
#define MCBS_RFIFO_STS_REG    (0x0000081C)
#define MCBS_BFIFO_DATA_REG   (0x00200000)

#define MCBSP1_DRR       (*(volatile uint32_t*)(MCBSP1_REG_BASE + 0x00000000))
#define MCBSP1_DXR       (*(volatile uint32_t*)(MCBSP1_REG_BASE + 0x00000004))
#define MCBSP1_SPCR      (*(volatile uint32_t*)(MCBSP1_REG_BASE + 0x00000008))
#define MCBSP1_RCR       (*(volatile uint32_t*)(MCBSP1_REG_BASE + 0x0000000C))
#define MCBSP1_XCR       (*(volatile uint32_t*)(MCBSP1_REG_BASE + 0x00000010))
#define MCBSP1_SRGR      (*(volatile uint32_t*)(MCBSP1_REG_BASE + 0x00000014))
#define MCBSP1_MCR       (*(volatile uint32_t*)(MCBSP1_REG_BASE + 0x00000018))
#define MCBSP1_RCER0     (*(volatile uint32_t*)(MCBSP1_REG_BASE + 0x0000001C))
#define MCBSP1_XCER0     (*(volatile uint32_t*)(MCBSP1_REG_BASE + 0x00000020))
#define MCBSP1_PCR       (*(volatile uint32_t*)(MCBSP1_REG_BASE + 0x00000024))
#define MCBSP1_RCER1     (*(volatile uint32_t*)(MCBSP1_REG_BASE + 0x00000028))
#define MCBSP1_XCER1     (*(volatile uint32_t*)(MCBSP1_REG_BASE + 0x0000002C))
#define MCBSP1_RCER2     (*(volatile uint32_t*)(MCBSP1_REG_BASE + 0x00000030))
#define MCBSP1_XCER2     (*(volatile uint32_t*)(MCBSP1_REG_BASE + 0x00000034))
#define MCBSP1_RCER3     (*(volatile uint32_t*)(MCBSP1_REG_BASE + 0x00000038))
#define MCBSP1_XCER3     (*(volatile uint32_t*)(MCBSP1_REG_BASE + 0x0000003C))

#define MCBSP2_DRR       (*(volatile uint32_t*)(MCBSP2_REG_BASE + 0x00000000))
#define MCBSP2_DXR       (*(volatile uint32_t*)(MCBSP2_REG_BASE + 0x00000004))
#define MCBSP2_SPCR      (*(volatile uint32_t*)(MCBSP2_REG_BASE + 0x00000008))
#define MCBSP2_RCR       (*(volatile uint32_t*)(MCBSP2_REG_BASE + 0x0000000C))
#define MCBSP2_XCR       (*(volatile uint32_t*)(MCBSP2_REG_BASE + 0x00000010))
#define MCBSP2_SRGR      (*(volatile uint32_t*)(MCBSP2_REG_BASE + 0x00000014))
#define MCBSP2_MCR       (*(volatile uint32_t*)(MCBSP2_REG_BASE + 0x00000018))
#define MCBSP2_RCER0     (*(volatile uint32_t*)(MCBSP2_REG_BASE + 0x0000001C))
#define MCBSP2_XCER0     (*(volatile uint32_t*)(MCBSP2_REG_BASE + 0x00000020))
#define MCBSP2_PCR       (*(volatile uint32_t*)(MCBSP2_REG_BASE + 0x00000024))
#define MCBSP2_RCER1     (*(volatile uint32_t*)(MCBSP2_REG_BASE + 0x00000028))
#define MCBSP2_XCER1     (*(volatile uint32_t*)(MCBSP2_REG_BASE + 0x0000002C))
#define MCBSP2_RCER2     (*(volatile uint32_t*)(MCBSP2_REG_BASE + 0x00000030))
#define MCBSP2_XCER2     (*(volatile uint32_t*)(MCBSP2_REG_BASE + 0x00000034))
#define MCBSP2_RCER3     (*(volatile uint32_t*)(MCBSP2_REG_BASE + 0x00000038))
#define MCBSP2_XCER3     (*(volatile uint32_t*)(MCBSP2_REG_BASE + 0x0000003C))

-------------------------------------------------------------------

/* McBSP Function Library Header File
*
*
*////////////////////////////////////////////////////////////

//Prototypes
//

void mcbspReset(unsigned int ulModule, unsigned char ulBlock);
void mcbspSetTxMode(unsigned int ulModule, unsigned char ulCLKXM, unsigned char ulCLKXP, unsigned char ulFSXM, unsigned char ulFSXP, unsigned char ulCYCLE, unsigned char ulDXENAMode, unsigned char ulEXTCLKGATE, unsigned char ulFSGM);
void mcbspSetRxMode(unsigned int ulModule, unsigned char ulCLKRM, unsigned char ulCLKRP, unsigned char ulFSRM, unsigned char ulFSRP, unsigned char ulCYCLE);
void mcbspRxFrameSetup(unsigned int ulModule, unsigned char ulRPHASE, unsigned char ulRREVERSE, unsigned char ulRDATDLY, unsigned char ulRFRLEN1, unsigned char ulRWDLEN1, unsigned char ulRFRLEN2, unsigned char ulRWDLEN2, unsigned char ulRJUST);
void mcbspTxFrameSetup(unsigned int ulModule, unsigned char ulXPHASE, unsigned char ulXREVERSE, unsigned char ulXDATDLY, unsigned char ulXFRLEN1, unsigned char ulXWDLEN1, unsigned char ulXFRLEN2, unsigned char ulXWDLEN2);
void mcbspSetupSrg(unsigned int ulModule, unsigned char ulSource, unsigned char ulCLKSP, unsigned char ulGSYNC, unsigned char ulFPER, unsigned char ulFWID, unsigned char ulCLKGDV);
void mcbspEnableFclk(unsigned int ulModule);
void mcbspDisableFclk(unsigned int ulModule);
void mcbspEnableIclk(unsigned int ulModule);
void mcbspDisableIclk(unsigned int ulModule);
void mcbspSelectClksSource(unsigned int ulModule, unsigned char ulSource);
void mcbspSet6Pin(unsigned int ulModule);
void mcbspSet4Pin(unsigned int ulModule);

void mcbspRemoveResetSrg(unsigned int ulModule);
void mcbspResetSrg(unsigned int ulModule);
void mcbspRemoveResetRx(unsigned int ulModule);
void mcbspResetRx(unsigned int ulModule);
void mcbspRemoveResetTx(unsigned int ulModule);
void mcbspResetTx(unsigned int ulModule);
void mcbspRemoveResetFsg(unsigned int ulModule);
void mcbspResetFsg(unsigned int ulModule);

void mcbspEnableTx(unsigned int ulModule);
void mcbspDisableTx(unsigned int ulModule);
void mcbspEnableRx(unsigned int ulModule);
void mcbspDisableRx(unsigned int ulModule);
void mcbspLoopback(unsigned int ulModule, unsigned char ulMode);
void mcbspDataPut(unsigned int ulModule, unsigned int ulData);
void mcbspDataGet(unsigned int ulModule, unsigned int *pulData);
void mcbspSetRxThresh(unsigned int ulModule, unsigned int ulThreshold);
void mcbspSetTxThresh(unsigned int ulModule, unsigned int ulThreshold);
void mcbspEnableTxDma(unsigned int ulModule);
void mcbspDisableTxDma(unsigned int ulModule);
void mcbspEnableRxDma(unsigned int ulModule);
void mcbspDisableRxDma(unsigned int ulModule);
unsigned int mcbspTxBuffStat(unsigned int ulModule);
unsigned int mcbspRxBuffStat(unsigned int ulModule);

void mcbspEnableWFIFO(unsigned int ulModule);
void mcbspEnableRFIFO(unsigned int ulModule);
void mcbspSetWFIFO(unsigned int ulModule,unsigned char ulNumDma, unsigned char ulNumEvent);
void mcbspSetRFIFO(unsigned int ulModule,unsigned char ulNumDma, unsigned char ulNumEvent);
void mcbspDataPutFifo(unsigned int ulModule, unsigned int *pulData, int nLength);
void mcbspDataGetFifo(unsigned int ulModule, unsigned int *pulData, int nLength);

unsigned char mcbspDataPutNoBlock(unsigned int ulModule, unsigned int ulData);
unsigned char mcbspDataGetNoBlock(unsigned int ulModule, unsigned int *pulData);
int mcbspEmptyRFifo(unsigned int ulModule);

// General defines
# define MCBSP1 MCBSP1_REG_BASE
# define MCBSP2 MCBSP2_REG_BASE

// mcbspSelectClksSource parameters
#define MCBSP_CLKS_PIN 1 // Set external mcbsp_clks pin as CLKS source
#define INTERNAL_FCLK 0 // Set intern FCLK as CLKS source

// mcbspRxFrameSetup & mcbspTxFrameSetup parameters
#define SINGLE_PHASE      0
#define DUAL_PHASE        0
#define RIGHT_JUST_ZERO   0
#define RIGHT_JUST_SIGN   1
#define LEFT_JUST_ZERO    2
#define MSB_FIRST         0
#define LSB_FIRST         1
#define DELAY_0BIT        0
#define DELAY_1BIT        1
#define DELAY_2BIT        2
#define WORD_8BITS        0
#define WORD_12BITS       1
#define WORD_16BITS       2
#define WORD_20BITS       3
#define WORD_24BITS       4
#define WORD_32BITS       5

// mcbspSelectSrgClockSource parameters
#define CLKS             0
#define CLKI             1
#define CLKR             2
#define CLKX             3
#define CLKS_RISE        0
#define CLKS_FALL        1
#define SRG_FREE         0
#define SRG_SYNC         1

// mcbspSetTxMode & mcbspSetRxMode parameters
#define CLK_EXTERNAL         0
#define CLK_INTERNAL         1
#define SYNC_EXTERNAL        0
#define SYNC_INTERNAL        1
#define SYNC_ACTIVE_HIGH     0
#define SYNC_ACTIVE_LOW      1
#define CLKX_DRIVE_RISE      0
#define CLKX_DRIVE_FALL      1
#define CLKR_SAMPLE_RISE     1
#define CLKR_SAMPLE_FALL     0
#define FULL_CYCLE           1
#define HALF_CYCLE           0
#define DXENA_OFF            0
#define DXENA_DLY1           1
#define DXENA_DLY2           2
#define DXENA_DLY3           3
#define DXENA_DLY4           4
#define XCLK_GATED           1
#define XCLK_FREE            0
#define FSX_GATED            0
#define FSX_FREE             1

// mcbspLoopback parameters
#define NO_LOOPBACK          0
#define DIGITAL_LOOPBACK     1
#define ANALOG_LOOPBACK      2

0 Sugumar Natarajan over 14 years ago in reply to ranchu

Intellectual 670 points

Hi Ran,

I will look into the problem and get back to you.

Regards,

N.Sugumar

0 Sugumar Natarajan over 14 years ago in reply to Sugumar Natarajan

Intellectual 670 points

Hi Ran,

Can you try configuring the Frame Sync mode to 'DXR-XSR copy' instead of the 'Frame Sync Generator' mode and see how it behaves?. If the Frame Sync is configured to be generated by the Frame Sync Generator, McBSP would continue to transmit the Data in the DXR register at the Frame Sync Frequency(FPER). Meanwhile, I will try to test your application and let you know.

Regards,

N.Sugumar

0 ranchu over 14 years ago in reply to Sugumar Natarajan

Guru 20755 points

Hi Natarajan,

Thank you very much for your assistance.
I reviewed the code, and I see that The FSGM bit is cleared when setting the transmitter (you can also view the code in my previous messeges). This means that I already work in 'DXR-XSR copy' mode.

Regards,

Ran

0 Sugumar Natarajan over 14 years ago in reply to ranchu

Intellectual 670 points

Hi Ran,

In the below code, FSGM is shifted by 12 but it is actually 28th bit of SRGR register. Anyway, the bit is cleared correctly before setting it.

SETBIT_REGL(ulModule + MCBSPLP_SRGR_REG, (ulFSGM<<12));

Can you dump the following registers and send the values ?

SPCR , Serial Port Control Register

SRGR, Sample rate generator register

PCR, Pin Configuration register

WFIFO and RFIFO control register.

Regards,

N.Sugumar

0 ranchu over 14 years ago in reply to Sugumar Natarajan

Guru 20755 points

Hi Natarajan,

You were right about the "bug" in the shift, I had the review the whole code and fix several errors in shifting.

It seems to work fine now, though I still need to check it thoroughly.

Many thanks!

Ran

0 qinbin wang over 12 years ago in reply to Sugumar Natarajan

Prodigy 220 points

hi Natarajan,

Recently my company is developing omapl138's receiving and sending data,now I could receive data correct for record but send.I try to test your ti's example code(mcbsp_test.c),there is a problem,please see http://e2e.ti.com/support/embedded/linux/f/354/t/251152.aspx

I do not change any test code,but it will be error,Could you have a look and help me ! SOS ,thank you!

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mcBSP Digital Loopback in OMAPL138