PROCESSOR-SDK-AM65X: Delay in loading R5 SPL

Matthew,

This looks to be similar to https://e2e.ti.com/support/processors/f/791/t/937393 though the delay you're reporting is quite a bit higher. Can you review and confirm the same? 

Best regards,

Dave

Hi Dave,

We don't have any long delays logging in to the Linux console, although there is a ~17s or so delay in the kernel timestamps on every boot. I believe it's due to the video driver(s) taking a long time to load and initialize.

Our issue seems to be related to the ROM bootloader and/or system firmware loading the very first R5 SPL. We apply power with the boot pins set to eMMC and see no output on the console for 2-3 minutes, then the board begins to boot 100% normally. This happens on around 3-5% of boots.

Thanks,
Matt McKee

Matt,

Thanks for clarifying. To confirm, you are seeing a delayed boot only on a cold start/PORz (i.e. power supply ramp-up and initial PORz), but not on warm reset or PORz without a power cycle?

And is the 3-5% on this cold start/PORz where occasionally it is delayed? Is it consistent on multiple boards?

Best regards,

Dave

Hi Dave,

We haven't thoroughly tested the warm reset or PORz without a power cycle scenario at this time. We do see this problem across multiple boards, but it doesn't seem to occur on every single board. Right now we've got at least one board that only fails to boot from eMMC when the PRU-ICSS-G or display driver fails to initialize in Linux. We have one board that fails to boot about 50% of the time, sometimes failing to boot as described above or timing out during the HS200 initialization in Linux.

Thanks,
Matt McKee

Dave,

We've performed more testing using the SR2.0 IDK and have noticed a few things: the IDK fails to boot in the same manner in ~1% of the attempts and if the IDK is placed in our temp chamber the board only boots at -10 degrees celcius. Any lower than that and the IDK completely fails to boot. Is this expected behavior?

Thanks,
Matt McKee

Additional temp chamber testing has been performed using the IDK. At 60C, the IDK fails to boot in the same manner as described above at a rate of around 3% of the boot attempts.

Matt,

Thanks for the added details. While SR2 silicon is currently in the sampling stage we do not expect to see failures as you describe.

There is a 180s timeout in the ROM boot, which could match to the 2-3 minute delay you're seeing meaning that the boot initially fails and is successful on retry after the timeout.

Have you already analyzed scope captures of your power ramp across voltages, clocks, and reset (PORz, PORz_OUT, MCU_PORz, MCU_PORz_OUT) and all are as expected and voltages are matching to the datasheet?

Best regards,

Dave

Hi Dave,

We've remeasured and analyzed our power sequencing and pretty much everything is within spec per the datasheet. Our RESETz might be held a little long than we'd like so we plan to swap out some capacitors to get it closer to the minimum but we don't think it's the cause of the issues we're seeing.

Can you speak to the temperature rating for the AM65x SR2.0 IDK and the fact that we're seeing issues booting from eMMC on the IDK? Is there a minimum time recommended between powering off and powering back on with the IDK?

Thanks,
Matt McKee

Hi Matt,

I tried reproducing at my end. I tried resetting 50 times manually and saw that R5 SPL traces came up in a flash.
So no such delay observed on SR2.0 IDK.

Matthew McKee said:

Can you speak to the temperature rating for the AM65x SR2.0 IDK and the fact that we're seeing issues booting from eMMC on the IDK? Is there a minimum time recommended between powering off and powering back on with the IDK?

cat /sys/class/thermal/thermal_zone*/type
mpu0_thermal
mpu1_thermal
mcu_thermal
root@am65xx-evm:~# cat /sys/class/thermal/thermal_zone*/temp
44600
45000
50600

Before you reset you can actually check the temperature if you believe it is too high.

The units for the above temperature is in milli degree centigrade.

Best Regards,
Keerthy