AM3352: About EMIF setting to DDR3L

user1201164

Part Number: AM3352

Hi,

We are receiving questions from our customers.
They have a custom board with DDR3L memory connected to AM3352 and are trying to use EMF_TOOL to determine the EMIF register settings.
In EMIF_TOOL, the value of the PWR_MGMT_CTRL register is fixed at 0x000002A0, and when this value is set on the actual machine, it is said that DDR3 cannot be accessed during normal operation.
They speculate that the refresh of the DDR controller and the Self Refresh behavior of DDR itself may be in conflict.

The following two questions.

1) Is it okay to set this register value to 0x000002A0 (bit10-8 is 0x2) during normal operation (ACTIVE mode)?
2) When the CPU transitions to RTC_ONLY mode and performs Self-Refresh operation only for DDR3 memory, please tell me the register setting value immediately before the transition.

The connection diagram of SoC and DDR3L and the Excel Sheet of EMIF_TOOL are attached.

Best Regards,

Kouji Nishigata

AM3352_DDR3L.pdf AM335x EMIF Tool.xlsx

over 5 years ago

0 Frank Livingston over 5 years ago

TI__Mastermind 30118 points

Hi Kouji,

Is the customer using Linux, or Processor-SDK-RTOS?

Thanks,
Frank

0 user1201164 over 5 years ago in reply to Frank Livingston

Expert 1770 points

Hi, Frank

Thank you for your reply.
They are using embedded Linux.

Best Regards,

Kouji Nishigata

0 Frank Livingston over 5 years ago in reply to user1201164

TI__Mastermind 30118 points

Hi Kouji,

I'll have this thread re-assigned to someone with Linux expertise. Thanks for your patience.

Regards,
Frank

0 Takayuki Miyazaki over 5 years ago in reply to Frank Livingston

TI__Genius 10120 points

Hello Experts,

Can we have your Expert's advice/comments on this, please?

I'm sorry to rush you but it is really appreciated your quick reply.

Best regards,

Miyazaki

0 Max Kross1 over 5 years ago in reply to Takayuki Miyazaki

TI__Intellectual 2180 points

Hello,

This has been reassigned to a Linux expert. You should hear from them soon.

Thanks,

Max

0 Schuyler Patton over 5 years ago in reply to Max Kross1

TI__Mastermind 41560 points

Hi,

The hardware expert is currently not available until later this week, we expect to have an answer by Thursday. We apologize for the delay.

Best Regards,

Schuyler

0 user1201164 over 5 years ago in reply to Schuyler Patton

Expert 1770 points

Hi,

I would like to know how things are going about the issue.

Best Regards,

Kouji Nishigata

0 Takayuki Miyazaki over 5 years ago in reply to Schuyler Patton

TI__Genius 10120 points

Hi Experts,

Can we have this current status, please?

We are sorry to rush you but it is really appreciated your quick reply.

Best regards,

Miyazaki

0 Takayuki Miyazaki over 5 years ago in reply to Takayuki Miyazaki

TI__Genius 10120 points

Hi Experts,

Customer is asking the current status of this inquiry , Can we have any comments on this, please?

Best regards, Miyazaki

0 JJD over 5 years ago in reply to Takayuki Miyazaki

TI__Guru* 96081 points

There may be some misinterpretation of terminology and what is supported. AM335x supports

a) DeepSleep0 mode: This is a mode which puts DDR in self-refresh, reduces MPU and CORE power supplies, turns the main oscillator OFF, and only the WKUP power domain is still on. Please see 8-13 in the TRM for further description

b)RTC only mode only the RTC remains active, all other power supplies are OFF, DDR contents are not maintained.

AM335x does not support RTC-only while keeping DDR in self refresh. The two modes mentioned above are supported in the Linux SDK.

Information on Linux driver support for power management can be found here: https://software-dl.ti.com/processor-sdk-linux/esd/docs/06_03_00_106/AM335X/linux/Foundational_Components/Kernel/Kernel_Drivers/Power_Management.html?highlight=power%20management

With a value of 0x2A0 in PWR_MGMT_CTRL, the DDR will go to self-refresh after a timeout specified in reg_sr_tim. If you want to disable this feature, you can set the PWR_MGMT_CTRL = 0xA0. However, when transitioning to DeepSleep0, the value of the register will need to be 0x2A0

Regards,

James

0 user1201164 over 5 years ago in reply to JJD

Expert 1770 points

Hi, James

Thank you for your answer.
When I told the customer, they understood as follows.
----------------------------------------------------------------------------------------------------
In normal operation (ACTIVE mode), reg_lp_mode of the PWR_MGMT_CTRL register should not be set to 0x2 in order to access DDR. (Must be 0x0)
----------------------------------------------------------------------------------------------------
Please confirm that there is no problem with this understanding.

Best Regards,

Kouji Nishigata

0 user1201164 over 5 years ago in reply to user1201164

Expert 1770 points

Hi, James

I would like to know how things are going about the issue.

Best Regards,

Kouji Nishigata

0 user1201164 over 5 years ago in reply to user1201164

Expert 1770 points

Hi,James

Do you know anything about the following issues?

----------------------------------------------------------------------------------------------------
In normal operation (ACTIVE mode), reg_lp_mode of the PWR_MGMT_CTRL register should not be set to 0x2 in order to access DDR. (Must be 0x0)
----------------------------------------------------------------------------------------------------

Customers say that if this is not a problem, it can be closed.
I thank you in advance for your reply.

Best Regards,

Kouji Nishigata

0 user1201164 over 5 years ago in reply to user1201164

Expert 1770 points

Hi,

I would like to know how things are going about the issue.

Best Regards,

Kouji Nishigata

0 JJD over 5 years ago in reply to user1201164

TI__Guru* 96081 points

Kouji, not exactly. Here is the behavior:

reg_lp_mode=2: the EMIF will put the DDR in self-refresh after an idle timeout (specified in SR_TIM) has expired. The EMIF will automatically exit self refresh when activity resumes

reg_lp_mode=0: the EMIF will never put DDR in self-refresh

In both cases, normal operation can occur. When the self refresh mode is enabled (0x2), the EMIF will automatically go in and out of self refresh based on idle time. If none of the masters are requesting data from the DDR, the EMIF will timeout and automatically put the DDR in self-refresh. This is a hardware feature to realize lower power. Once a master requests data from the DDR, the EMIF will automatically exit self-refresh and complete the transaction. The only drawback is higher latency when activity resumes

If you want your application to go in and out of self-refresh in more of a controlled manner via software, then use reg_lp_mode as you describe (set to 0 for normal operation, set to 0x2 when you want to enter self-refresh)

Regards,

James

0 user1201164 over 5 years ago in reply to JJD

Expert 1770 points

Hi, James

thank you for your answer.
We are asking our customers if this is okay, so please be patient.

Best Regards,

Kouji Nishigata

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AM3352: About EMIF setting to DDR3L