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Original question:

AM5726: AM5726

AM5726: AM5726

Ioan Marusca
Intellectual 260 points
Part Number: AM5726

The Bit EXT_EN is set to 0 in our system (checked it with raw memory read from SL_MACCONTROL register and value is 0x000000A1).

The EMAC_RX_ISR_PER_MSEC_DEFAULT can't be found in the path you have indicated. We are using RTLinux.

In anycase I was expecting that the enabling automatic pooling on behalf of GMAC ports to be a bit in the MDIO control register MDIO_CONTROL.

So ... Is it possible to turn off the automatic pooling but keep the user SMI access ?  

  • 0 in reply to Ioan Marusca
    TI__Genius 14680 points

    Ioan,

    In the other e2e post we were addressing with a pdk example. For Linux, can you try leveraging a "fixed-link" configuration to remove the auto-negotiation steps?

    See some details and pointers in https://e2e.ti.com/support/processors/f/791/p/883618/3276983

    I'll check if there's any specific guidance for disabling automatic polling on the AM57. Per http://e2e.ti.com/support/processors/f/791/t/461714 there is not.

    Best regards,

    Dave

  • 0 in reply to Dave Bell
    Intellectual 260 points

    Dave,

    I guess that the implementation has not changed between generations of TI CPUs, so disabling the automatic pooling and still using the MDIO to issue user driven operations is not possible.

    It would be good to document this and also provide detailed transaction waveforms in the TRMs for automatic and user mdio transactions.

    Are the mdio (gmac and pru) software "implemented" in the pru ? Can they be upgraded ?

    The maximum clock frequency for MDC (gmac and pru) is 2.5MHz. This is quite low comparing to other devices (phys/switches/CPUs) and has impact on user software response when it needs to access large array of registers (as an example ... reading of all 32 bit statistics counter from a with 16/24 ports switch). What is the need to be so slow ?

  • 0 in reply to Ioan Marusca
    TI__Genius 14680 points

    Ioan,

    The MDIO modules for both the GMAC and the PRU-ICSS are implemented in hardware.

    I do not see a mechanism to disable auto-polling in the AM57. There are bit-bang drivers under Linux as a potential option to consider, but these are not developed or tested by TI.

    Best regards,

    Dave

  • 0 in reply to Dave Bell
    Intellectual 260 points

    MDC (gmac and pru) is 2.5MHz. This is quite slow comparing to other devices with MDIO interfaces (phys/switches/CPUs) and has impact on user software response when it needs to access large array of registers (as an example ... reading of all 32 bit statistics counter from a with 16/24 ports switch). What is the need to be so slow ?

  • 0 in reply to Ioan Marusca
    TI__Genius 14680 points

    Ioan,

    The MDIO hardware module isn't specifically limited to 2.5MHz operation, though we do not characterize or test beyond what is specified in the datasheet. The datasheet value matches to what is defined in IEEE standard Clause 22 and Clause 45, where the max MDIO speed is 2.5Mhz. See section 22.2.2.11 MDC (management data clock).

    Best regards,

    Dave

  • 0 in reply to Dave Bell
    Intellectual 260 points

    Using a scope I see 32 idle clocks regardless of the value of PREAMBLE bit (register MDIO_CONTROL). On a rare occasion, when I trigger a user access using MDIO_USERACCESS register, I can see preamble being suppressed for just that one transaction.

    Can you describe in detail the expected behavior regarding preamble and preamble suppression ? To what transactions does it apply ?

  • 0 in reply to Ioan Marusca
    TI__Genius 14680 points

    Ioan,

    The MDIO will initialize the link when the enable is set, if you toggle the enable then every time you set it a 32 cycle initialization sequence is issued.
    If you do not toggle the enable, the 32 bit preamble is suppressed based on the preamble bit.

    Best regards,

    Dave

  • 0 in reply to Dave Bell
    Intellectual 260 points

    Below is a sequence of commands to change the MDIO bits as you suggested, but always I see 65 clocks between successive start bits of MDIO transactions (independent of PREAMBLE status). Shouldn't it be 33 clocks when PREAMBLE=1 and 65 when PREAMBLE=0 ?

    BIST:/root# memtool md -l 0x48485004
    48485004: 81100031 00000003 00000002 00000003 1...............
    48485014: 00000000 00000000 00000000 00000001 ................
    48485024: 00000000 00000000 00000000 00000000 ................
    48485034: 00000000 00000000 00000000 00000000 ................
    48485044: 00000000 00000000 00000000 00000000 ................
    48485054: 00000000 00000000 00000000 00000000 ................
    48485064: 00000000 00000000 00000000 00000000 ................
    48485074: 00000000 00000000 00000000 6200016d ............m..b
    48485084: 00000000 00000000 00000000 00000000 ................
    48485094: 00000000 00000000 00000000 00000000 ................
    484850a4: 00000000 00000000 00000000 00000000 ................
    484850b4: 00000000 00000000 00000000 00000000 ................
    484850c4: 00000000 00000000 00000000 00000000 ................
    484850d4: 00000000 00000000 00000000 00000000 ................
    484850e4: 00000000 00000000 00000000 00000000 ................
    484850f4: 00000000 00000000 00000000 00000000 ................
    BIST:/root# memtool mw -l 0x48485004 0x41100031

    BIST:/root# memtool md -l 0x48485004

    48485004: 41100031 00000003 00000002 00000003 1..A............
    48485014: 00000000 00000000 00000000 00000001 ................
    48485024: 00000000 00000000 00000000 00000000 ................
    48485034: 00000000 00000000 00000000 00000000 ................
    48485044: 00000000 00000000 00000000 00000000 ................
    48485054: 00000000 00000000 00000000 00000000 ................
    48485064: 00000000 00000000 00000000 00000000 ................
    48485074: 00000000 00000000 00000000 6200016d ............m..b
    48485084: 00000000 00000000 00000000 00000000 ................
    48485094: 00000000 00000000 00000000 00000000 ................
    484850a4: 00000000 00000000 00000000 00000000 ................
    484850b4: 00000000 00000000 00000000 00000000 ................
    484850c4: 00000000 00000000 00000000 00000000 ................
    484850d4: 00000000 00000000 00000000 00000000 ................
    484850e4: 00000000 00000000 00000000 00000000 ................
    484850f4: 00000000 00000000 00000000 00000000 ................

    (at this moment I checked with scope and seen 65 clocks between successive MDIO reads initiated by the MDIO hardware, expecting 33 clocks)

    BIST:/root# memtool mw -l 0x48485004 0x01100031
    BIST:/root# memtool md -l 0x48485004
    48485004: 81100031 00000003 00000002 00000003 1...............
    48485014: 00000000 00000000 00000000 00000001 ................
    48485024: 00000000 00000000 00000000 00000000 ................
    48485034: 00000000 00000000 00000000 00000000 ................
    48485044: 00000000 00000000 00000000 00000000 ................
    48485054: 00000000 00000000 00000000 00000000 ................
    48485064: 00000000 00000000 00000000 00000000 ................
    48485074: 00000000 00000000 00000000 6200016d ............m..b
    48485084: 00000000 00000000 00000000 00000000 ................
    48485094: 00000000 00000000 00000000 00000000 ................
    484850a4: 00000000 00000000 00000000 00000000 ................
    484850b4: 00000000 00000000 00000000 00000000 ................
    484850c4: 00000000 00000000 00000000 00000000 ................
    484850d4: 00000000 00000000 00000000 00000000 ................
    484850e4: 00000000 00000000 00000000 00000000 ................
    484850f4: 00000000 00000000 00000000 00000000 ................
    BIST:/root# memtool mw -l 0x48485004 0x41000031
    BIST:/root# memtool md -l 0x48485004
    48485004: 41000031 00000003 00000002 00000003 1..A............
    48485014: 00000000 00000000 00000000 00000001 ................
    48485024: 00000000 00000000 00000000 00000000 ................
    48485034: 00000000 00000000 00000000 00000000 ................
    48485044: 00000000 00000000 00000000 00000000 ................
    48485054: 00000000 00000000 00000000 00000000 ................
    48485064: 00000000 00000000 00000000 00000000 ................
    48485074: 00000000 00000000 00000000 6200016d ............m..b
    48485084: 00000000 00000000 00000000 00000000 ................
    48485094: 00000000 00000000 00000000 00000000 ................
    484850a4: 00000000 00000000 00000000 00000000 ................
    484850b4: 00000000 00000000 00000000 00000000 ................
    484850c4: 00000000 00000000 00000000 00000000 ................
    484850d4: 00000000 00000000 00000000 00000000 ................
    484850e4: 00000000 00000000 00000000 00000000 ................
    484850f4: 00000000 00000000 00000000 00000000 ................
    BIST:/root#

    (at this moment I checked with scope and seen 65 clocks between successive MDIO reads initiated by the MDIO hardware)

  • 0 in reply to Ioan Marusca
    TI__Genius 14680 points

    Ioan,

    The preempt bit enables smart preamble function. But PHYs can specify preamble requirements, that is bit 6 of the PHY status register (1) can demand full preamble.

    If the smart preamble it is set and ALL the PHYs have bit 6 as a ‘1’, then the preamble will be suppressed.

    But if a PHY Ack changes that is a PHY ack with preamble and does not respond to the next request, the pre-amble is enabled until all the PHYs are polled.
    That is every time a PHY changes it active status the preamble will be enabled for the poll cycle.

    Preamble is automatically enabled for
    • Any PHY had the suppress status.preamble(1.6) ==0
    o If one of the polled PHYs has the status.preamble(1.6) ==0, preambles will not be suppressed.
    • Polling register is ‘0’
    o If you do not have any PHYs in the polling register, pre-ambles will always be sent.
    • Enable is ‘0’
    o If you disable the MDIO, the first 32 polling cycle will have the preamble enabled.
    • Any PHY alive status changes.
    o That is if a PHY acks a polling cycle and then does not ack the next polling cycle the preamble is sent for the next polling cycle.

    We did find that you must poll PHY 31 for the short preamble to work. If you do not poll PHY 31, the MDIO logic never evaluates the use_preamble signal. But :

    1)      If the PHY does not support suppressed preambles OR

    2)      Anytime a PHY changes it alive status, that is acks with preamble and does not ack on suppressed preamble

    As a reference from IEEE spec, Clause 22 status register:

    1.6 MF Preamble Suppression

    1 = PHY will accept management frames with preamble suppressed

    0 = PHY will not accept management frames with preamble suppressed RO

    Best regards,

    Dave