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TMDXICE110: Power Off Sequence

Hirotsugu Kobayashi
Mastermind 9720 points

Part Number: TMDXICE110
Other Parts Discussed in Thread: TPS650250, AMIC110

Hi team,

In the TMDXICE110 circuit, is the TPS650250 UVLO turned off before the power down sequence circuit is activated?

AMIC110_Poff.pptx

  • 0
    TI__Mastermind 42545 points

    Hi Hirotsugu-san,

    The UVLO signal is generated within the TPS650250 by an internal voltage comparator when the VCC voltage drops below a specified level.  Are you asking if the threshold is crossed before the power down sequence is activated?

    Regards, Bill 

  • 0 in reply to Bill Taboada
    Mastermind 9720 points

    Hi Bill-san

    The circuit of TMDXICE110 is designed according to AN (SLVU731),

    but it does not have the off-sequence like AN because there is no SYS_EN signal.

    Is there any problem with the specifications that 5V drops and turns off with UVLO of TPS650250?

    Best Regards,

  • 0 in reply to Hirotsugu Kobayashi
    TI__Mastermind 42545 points

    Hi Hirotsugu-san,

    The SYS_EN signal is generated from an an on/off switch or an equivalent circuit and is used to generate the enables.  The TMDXICE110 board doesn't use a switch and is powered on and off based on the +5V input voltage.  You are correct that the UVLO may not be active in a circuit where the SYS_EN is controlled by a switch but that wasn't taken into account when designing the TMDXICE110.  We haven't seen any issues but if you are concerned you can implement an external voltage monitor which will generate a SYS_EN going low at a higher voltage than the one used by the UVLO circuit as the +5V decays.  That will initiate the power down before the UVLO circuit effects the LDOs.

    Regards, Bill