AM6548: Setup for SERDES0 = PCIe0 Lane 0, SERDES1 = PCIe1 Lane0

Hi,

I have my two serdes channels connected to two different devices. What modifications are needed to get SERDES0 = PCIe0 Lane 0, SERDES1 = PCIe1 Lane0?

I've been trying to modify the existing 2 lane pcie0 k3_am654-pcie-usb2.dtso overlay to do this, but in most cases where I've attempted to declare the serdes1 as <&serdes1 PHY_TYPE_PCIE 0> (from ti,phy-am654-serdes.txt), I lose the PCIe 1 channel on boot and PCIe0 does not connect to the device downstream. With the original dtso, the device on serdes1 connected reasonably reliably. Serdes0 does not come up unless the serdes1 device did not come up. 

My best guess so far is that I can leave the &serdes0 declaration as is, delete the &serdes1 declaration to go to the default in the main.dtsi so that assigned-clock-parents is no longer <&serdes0 AM654_SERDES_RO_REFCLK>, split the pcie0_rc into a pcie0_rc and pcie1_rc, and split the pcie0_ep to pcie0_ep and pcie1_ep. I also have a second reset line available for pcie1. Copied at the bottom is the dts with these modifications, but it didn't work.

I'm definitely missing something, any pointers on where to look next would be appreciated. 

Thanks,

Andrea

// SPDX-License-Identifier: GPL-2.0
/**
* DT overlay for SERDES personality card: 2lane PCIe + USB2.0 Host on AM654 EVM
*
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
*/

/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/phy/phy-am654-serdes.h>
#include <dt-bindings/pinctrl/k3.h>

&serdes0 {
assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>, <&serdes0 AM654_SERDES_RO_REFCLK>;
assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>, <&k3_clks 153 4>;
status = "okay";
};

&pcie0_rc {
num-lanes = <1>;
phys = <&serdes0 PHY_TYPE_PCIE 1>
phy-names = "pcie-phy0"";
reset-gpios = <&pca9555 15 GPIO_ACTIVE_HIGH>;
status = "okay";
};

&pcie1_rc {
num-lanes = <1>;
phys = <&serdes1 PHY_TYPE_PCIE 0>;
phy-names =  "pcie-phy1";
reset-gpios = <&pca9555 5 GPIO_ACTIVE_HIGH>;
status = "okay";
};

&pcie0_ep {
num-lanes = <1>;
phys = <&serdes0 PHY_TYPE_PCIE 1>;
phy-names = "pcie-phy0";
};

&pcie1_ep {
num-lanes = <1>;
phys = <&serdes1 PHY_TYPE_PCIE 0>;
phy-names = "pcie-phy1";
};

&main_pmx0 {
usb0_pins_default: usb0_pins_default {
pinctrl-single,pins = <
AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
>;
};
};

&dwc3_0 {
status = "okay";
};

&usb0_phy {
status = "okay";
};

&usb0 {
pinctrl-names = "default";
pinctrl-0 = <&usb0_pins_default>;
dr_mode = "host";
};