TDA4VM: RMII REF CLK WITH 3 PHY CONNECTION

Hi TI Support Team

I want to know if this ticket have assign to TDA4 process expert ?

Hope to get your comments in this week

Thanks

Yutai

Option 1 is no.  Option 2 is yes.  Option 3 might be yes – PHY supports multiple output pins for REF_CLK.

The key for options 2/3 is to make sure to include the clock propagation and routing delays into the timing analysis for each interface. The setup/hold timings for all three RMII interfaces must be met when timing all three data busses against the common REF_CLK input to the SoC.

1. The REF CLK in TDA4 side used for all TDA4 RMII interface.  Is it correct ? 

2. Does TDA4 can used REF_CLK or data frame to sync RMII TX/RX data? 

Thanks

Yutai

There’s a MCU_RMII1_REF_CLK for the MCU domain CPSW2G and a RMII_REF_CLK for the Main domain CPSW9G.

The REF_CLKs are used to latch the data as shown in the timing tables 

Can we use the TDA4 CLK OUT (50MHz) to sync TDA4 REF_CLK and others PHY REF_CLK

Thanks

Yutai

Yes - MCU_CLKOUT0 assuming you buffer the clock to route to multiple destinations.

That means Main domain (CPSW9G) signal CLKOUT (pin AA25 / AJ28 /Y29) or WKUP/mcu domain signal MCU_CLK_OUT0 (pin H27) both used the sync TDA4 RMII and PHY RMII REF CLK.

Question:

1. How about the CLKOUT driver strength, does it can driver 3 PHY and route back to TDA4 RMII REF CLK.

2. If we must add external clock buffer ?

Thanks

Yutai