PROCESSOR-SDK-DRA8X-TDA4X: TDA4X CSITX port output mipi signal with VS DE PCLK but no HS

Hi Jason,

Sorry i did not get the question. You are comparing serial interface vs parallel interface. Both are different. Also CSITX output is compliant to MIPI standard, it sends CSI2 packets containing line data..  It is different from parallel output..

Rgds,

Brijesh 

Hi Brijesh,

       Thanks for your reply, but we see in tda4, csitx init below, the vBlank and hBlank are initialized, if the CSITX do not transfer the HS/VS by mipi, why they are initialized?  For our hdmi display needs the HS/VS/DE/PCLK，but we only get the VS/DE/PCLK signal from Deserializer, the signal from tda4 csitx port can't be display. The transmission link is :  TDA4 CSITX PORT--> GMSL1 Serializer-->Coaxial cable-->GMSL1 Deserializer-->TFP410-->HDMI display

Regards,

Jason

void tivx_csitx_params_init(tivx_csitx_params_t *prms)
{
uint32_t cnt, loopCnt;

if (NULL != prms)
{
prms->numInst = 1u;
prms->numCh = 0u;

for (loopCnt = 0U ; loopCnt < TIVX_CSITX_MAX_INST ; loopCnt++)
{
prms->instId[loopCnt] = loopCnt;
prms->instCfg[loopCnt].rxCompEnable = (uint32_t)vx_true_e;
prms->instCfg[loopCnt].rxv1p3MapEnable = (uint32_t)vx_true_e;
prms->instCfg[loopCnt].laneBandSpeed = TIVX_CSITX_LANE_BAND_SPEED_770_TO_870_MBPS;
prms->instCfg[loopCnt].numDataLanes = 5u;
for (cnt = 0u; cnt < prms->instCfg[loopCnt].numDataLanes; cnt ++)
{
prms->instCfg[loopCnt].lanePolarityCtrl[cnt] = 0u;
}
prms->instCfg[loopCnt].vBlank = 22U;
prms->instCfg[loopCnt].hBlank = 40U;
prms->instCfg[loopCnt].startDelayPeriod = 40U;
}
for (cnt = 0u; cnt < TIVX_CSITX_MAX_CH; cnt ++)
{
prms->chVcNum[cnt] = cnt;
prms->chInstMap[cnt] = 0U;
}
}
}

Hi Jason,

Those parameters are used to include blanking periods, but not HS signal. 

I would suggest to refer to CSI2 specs. CSI2 output is packetized output.. 

Regards,

Brijesh

Hi Brijesh,

      You mean CSI2 output not include the HS signal?And the csitx serial interface(mipi output) can't transfer the HS signal? So why the Deserializer can detect the VS/DE/PCLK, but only no HS.By the way,  the Deserializer parallel output  to the TFP410, which need the HSYNC, VSYNC, DE, and PCLK.

      Our ultimate goal is to use CSITX port to transfer the RGB888 data to the other board to display, which use the TFP410 to HDMI display, cound you tell me a reliable scheme?

Regards,

Jason

Hi Jason,

Can you check in deserializer? how does it generate VS/DE signals? 

Regards,

Brijesh

Hi Jason,

VBLANK parameter is not used currently. So you could ignore these parameters.. 

In CSI, i think there is no concept of HS signal. CSI sends line start, line end as line markers and then frame start & frame end as frame marker.. 

I think Deserializer generates DE signal from these markers, but i am not sure if/how deserializer can generate HS signal from it. Can you check in deserializer? 

Rgds,

Brijesh

Hi Brijesh,

       Thanks very much, now I found the Serializer could produce the HS signal, we will confirm this further.

Regards,

Jason

Thanks Jason for the update. Sure, if deserializer can generate HS output, it would be best.

Regards,

Brijesh