KeyStone II 10 Gigabit Ethernet(3-port) itself QoS capabilities

Hi Nikhil,

I thought it is already under processors forum, I opened you suggested link, then I can see this ticket which I created.

Hi Libing,

Apologies for the confusion. We have re-routed the question to the C6000 DSP team and you will receive a response to your query as soon as possible.

Thank you,

Nikhil

Hi Libing,

Aravind from DSP team here. Let me check with IP experts and get back to you on this.

Thanks

Hi Libing,

I got answers from the IP team for your questions. 

1. Why missing another (RX_PRI_MAP) for P1&P2?
   1. They are not missing: The receive packet mapping for these ports is in the MAC sliver registers. Please see below:

   2. 0x424	SL1_Rx_Pri_Map	CPXMAX_SL1 Rx Pkt Priority to Header Priority Mapping Reg
      0x464	SL2_Rx_Pri_Map	CPXMAX_SL2 Rx Pkt Priority to Header Priority Mapping Reg

2. Do these two Ethernet ports(P1&P2) support packet priority handling?
   1. Yes
3. What’s packet priority handling algorism? Does it mean strict priority scheduling？
   1. Can you please provide the ID version register of the CPSW you are using? The default is strict priority in every CPSW.
4. On the Queue size per Priority questions, 
   1. There is a typo as you highlighted. It should 2560 (instead of 2056). You cannot allocate to individual queues, but you can limit the number of allocated blocks that each queue receives.
   2. Since TX_BLK_CNT bit fields are BIT9-BIT13, and from register memory dump, the value is 0x00000302, then it looks both P1&P2 TX_BLK_CNT are set to “1”:
      1. What’s the memory block size?
      2. The number of memory blocks is “1”, what’s the amount of memory represent for?
      3.  Are BIT9-BIT13 correct for TX_BLK_CNT bit fields
      • ANS: Can you please share the ID version register of CPSW (CPSW_IDVER) value to answer this for certain, but this register indicates the number of blocks that are currently allocated in TX and RX at the moment.  It is read only and is intended to give an indication of block usage.  Please note that, this is a status register and not a configuration register.

        • Doc: https://www.ti.com/lit/ug/spruhj5/spruhj5.pdf
          Table 3-2 10 Gigabit Ethernet Subsystem Complete Register Listing (Part 3 of 8)
          01000h 10 GbE Switch CPSW_IDVER 10GbE switch identification and version register Section 3.6.1.1

Hi Aravind,

Thanks for your feedback, the ID version register of CPSW (CPSW_IDVER) should be: (Adr: 0x02f01000 4ee30101), and ES_SS_IDVER should be: (Adr: 0x02f00000 4ee42140).

Could you let me know how to limit the number of allocated blocks that each queue receives? E,g.:

1. Can we limit the number of allocated blocks both for TX and RX queues, per channel or in total for all channels? If yes, could you let know me how?  
   1. Which registers? Can they be modified in running time and take effective immediately?
   2. How to check/verify the limitation number is in right value?

Could you continue answer my questions for :

Since TX_BLK_CNT bit fields are BIT9-BIT13, and from register memory dump, the value is 0x00000302, then it looks both P1&P2 TX_BLK_CNT are set to “1”:

1. What’s the memory block size?
2. The number of memory blocks is “1”, what’s the amount of memory represent for?
3.  Are BIT9-BIT13 correct for TX_BLK_CNT bit fields

Hi Libing,

1. Regarding limiting the number of allocated blocks for Tx and Rx queues:

This is an early version of the CPSW and there is no mechanism to limit the number of blocks in each queue or for transmit/receive.  There are 20 4k blocks (80k total) on transmit, and 16 1k blocks (16k total) for receive.

2. Regarding  the value 0x00000302

The blk count location is a status and not a configuration.  It indicates how many blocks are currently allocated to transmit and receive.  The 0x0302 number indicates that receive has 2 of the 16 blocks currently allocated and transmit has 3 of the 20 blocks currently allocated (which may be across all priorities).

Thanks