PROCESSOR-SDK-DRA8X-TDA4X: TDA4, NVMe SSD on PCIe3

Part Number: PROCESSOR-SDK-DRA8X-TDA4X

Hi,

I'm working on a custom board with a TDA4 SoC, using Processor SDK 7.0.
I'm trying to bring up the serdes3 in PCIe mode. There's a NVMe SSD connected to serdes3, both lanes of the serdes3 are used by the SSD.
On the TDA4 EVM the first lane of serdes3 is used by USB. I removed that from the device tree.

The Linux kernel PCIe driver times out trying to bring up PCIe3:

[    4.853657] j721e-pcie 2930000.pcie: Timed out while waiting for link
[    4.860088] j721e-pcie 2930000.pcie: PCIe link never came up
[    4.865737] j721e-pcie 2930000.pcie: host bridge /interconnect@100000/pcie@2930000 ranges:
[    4.873987] j721e-pcie 2930000.pcie: Parsing ranges property...
[    4.874005] j721e-pcie 2930000.pcie:    IO 0x4410001000..0x4410010fff -> 0x00001000
[    4.881650] j721e-pcie 2930000.pcie:   MEM 0x4410011000..0x4417ffffff -> 0x00011000
[    4.925080] j721e-pcie 2930000.pcie: PCI host bridge to bus 0001:00

Do you have a device tree example that uses serdes3 in PCIe mode?

Here's the part of the device tree that is related to this subject:

&usb_serdes_mux {
	idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */
	mux-reg-masks = <0x4000 0x0000000>, /* USB0 to SERDES0 mux */
			<0x4010 0x0000000>; /* USB1 to SERDES1 mux */
};

&serdes_ln_ctrl {
	mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lanes not used */
			<0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lanes not used */
			<0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lanes not used */
			<0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lanes PCIE3 */
			<0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
					/* SERDES4 lane0/1/2/3 select */
	idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
		      <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
		      <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
		      <SERDES3_LANE0_PCIE3_LANE0>, <SERDES3_LANE1_PCIE3_LANE1>,
		      <SERDES4_LANE0_QSGMII_LANE5>, <SERDES4_LANE1_QSGMII_LANE6>, <SERDES4_LANE2_QSGMII_LANE7>, <SERDES4_LANE3_QSGMII_LANE8>;
};

&serdes_wiz3 {
	lane0-mode = <PHY_TYPE_PCIE>;
	lane1-mode = <PHY_TYPE_PCIE>;
};

&serdes3 {
	serdes3_pcie_link: link@0 {
		reg = <0>;
		cdns,num-lanes = <2>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
		resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
	};
};

&pcie3_rc {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pcie3_pins_default>;
	reset-gpios = <&main_gpio0 40 GPIO_ACTIVE_LOW>;
	phys = <&serdes3_pcie_link>;
	phy-names = "pcie_phy";
	num-lanes = <2>;
};

Thank you.