TDA4VM: DDR 64bit address range

Ryan Stark

Part Number: TDA4VM

Is there anyway to access all ddr as a sequential physical address space. Looks like first 2gby is always at 0x8000_0000 and next address is 0x8_0000_0000 but "The first 2 GB of this region are inaccessible." so it is really 0x8_8000_0000. I don't want to use the a72 MMU since peripherals and other cores would need a virt to phy conversion.

On am6 I could use CTRLMMR0_MCU_MSMC_CFG to map that first 2gby up to 0x8_0000_0000 but I don't see that option on j7.

over 4 years ago

0 Kevin S over 4 years ago

TI__Mastermind 40430 points

Hi Ryan,

Please see the link below with similar question. Note that you should be able to see the full 4GB from 0x8 8000 0000 - 0x9 7FFF FFFF.

e2e.ti.com/.../976016

Best regards,
Kevin

0 Ryan Stark over 4 years ago in reply to Kevin S

Expert 2930 points

Does that work with ECC enabled? I can see the duplicate data at 0x8E38E3900 but get ecc errors when modifying. Is there a way to make that work? Probably would also prefer 4kb aligned address be 4kb aligned on ddr.

0 Kevin S over 4 years ago in reply to Ryan Stark

TI__Mastermind 40430 points

Hi Ryan,

Is this question still open?

Thanks,
Kevin

0 Ryan Stark over 4 years ago in reply to Kevin S

Expert 2930 points

Yes. Can you confirm there is no way to get a sequential address space if ecc is enabled and without using the a72 mmu.

0 Kevin S over 4 years ago in reply to Ryan Stark

TI__Mastermind 40430 points

Hi Ryan,

I received the following statement from our design team:

Yes, the system address will not align with the DRAM physical address. However, this translation is done in HW by the DDR bridge. So the system/application should see contiguous address space, just 1/9^th less than the actual DRAM size.

Let me know if that answers your question or whether further clarification is needed.

Thanks,
Kevin

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TDA4VM: DDR 64bit address range