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AM5726: PCIe driver

Part Number: AM5726
Other Parts Discussed in Thread: AM5746

Hi Sitara support Team,

My customer is experiencing the following phenomenon with the custom board,
and would like an answer to a question about the workaround.

* I had misspelled the part number.
  The correct part number is AM5746.

-Software version:
TI-provided PCIe driver included in Linux kernel obtained from TI-provided git repository.

git repo URL: git://
git branch: processor-sdk-linux-rt-4.19.y

Confirmed git revs:
1201454b51e0a2a4fc2f7b68780b05024a31f4bc (old)
a242ccf3f13f03d41d521411ce2cc09775c873a2 (repo head at the moment)

After booting the OS (Linux), when rebooting with the "reboot" or "shutdown -r now" command,
the system does not reboot and hangs in the middle of the reboot process.
This occurs with high frequency.

#The H/W reset signal (RSTOUTn) is not output when the problem occurs.
# When this happens, the JTAG connection to the SoC is lost.
#The error like "cpu pipeline stalled" occurs.

During shutdown
 1. The driver software drops the link of the PHY for PCIe.
  → Address number : 0x5100 2104
 2. Execute the process to stop the PHY.
   → Address number : 0x4a00 3c40
       Set CTRL_CORE_PHY_POWER_PCIESS1[15:14] to 0b00.

If the above process is done in order, but there is not enough time interval, it will hang up.

Delay the process for a few ms after dropping the PHY link.
The shortest we have seen is 5 ms, and since it is only executed at shutdown or when an error occurs,
we set the workaround to 5 ms.

We are not sure why the workaround is working.
Can you please explain the cause and clarification?

Best regards,

  • Hi Sitara support Team,

    I referred to the following thread.

    Am I correct in understanding that the customer's workaround, as described in B.C.'s post of March 24, 2020,
    is being able to adjust the delay so that the PCIe TX signals on both sides of the link start toggling at the same time?
    Also, does the customer need to look at the PCIe AC coupling caps on the board to observe the alignment accurately?

    Please let us know if there is any other information you need to help us answer this question.

    Best regards,

  • Hi Sitara support Team,

    I need to give my customer a date when I can get an answer,
    so could you please just give us a schedule?

    Best regards,

  • Hi Sitara support team,

    Could someone please reply to this post?
    Please let me just check the progress of the response.

    Best regards,

  • Hi Kanae, 

    Sorry for the delay in response.

    I will check the shutdown sequence with our driver team. I suspect the controller has not been reset before the PHY lanes are disabled, and there are standing transactions in the system that caused the hang. 

    could you ask the customer to do an experiment by first shutdown the PCIe, by issuing one of the command below on Linux console before issuing shutdown:

     echo 0 > /sys/bus/pci/devices/$NUMBER/power

      echo "1" > /sys/bus/pci/devices/$NUMBER/remove

    This is just an experiment as I understand the shutdown may be triggered by watchdog. 



  • Kanae, 

    Also our driver team suggested to try: 

    "Remove dra7xx_pcie_disable_phy() in shutdown"

    and see if the system still hangs.



  • Hi Jian,

    Thank you for your support.

    I will ask my customer to review your proposal and post the results here.

    Best regards,