Other Parts Discussed in Thread: AM5746
Hi Sitara support Team,
My customer is experiencing the following phenomenon with the custom board,
and would like an answer to a question about the workaround.
* I had misspelled the part number.
The correct part number is AM5746.
-Software version:
TI-provided PCIe driver included in Linux kernel obtained from TI-provided git repository.
git repo URL: git://git.ti.com/processor-sdk/processor-sdk-linux.git
git branch: processor-sdk-linux-rt-4.19.y
Confirmed git revs:
1201454b51e0a2a4fc2f7b68780b05024a31f4bc (old)
a242ccf3f13f03d41d521411ce2cc09775c873a2 (repo head at the moment)
-Phenomenon
After booting the OS (Linux), when rebooting with the "reboot" or "shutdown -r now" command,
the system does not reboot and hangs in the middle of the reboot process.
This occurs with high frequency.
#The H/W reset signal (RSTOUTn) is not output when the problem occurs.
# When this happens, the JTAG connection to the SoC is lost.
#The error like "cpu pipeline stalled" occurs.
-Occurrence
During shutdown
1. The driver software drops the link of the PHY for PCIe.
→ Address number : 0x5100 2104
PCIECTRL_TI_CONF_DEVICE_CMD[0] Set LTSSM_EN to 0b0.
2. Execute the process to stop the PHY.
→ Address number : 0x4a00 3c40
Set CTRL_CORE_PHY_POWER_PCIESS1[15:14] to 0b00.
If the above process is done in order, but there is not enough time interval, it will hang up.
-Workaround.
Delay the process for a few ms after dropping the PHY link.
The shortest we have seen is 5 ms, and since it is only executed at shutdown or when an error occurs,
we set the workaround to 5 ms.
-Question
We are not sure why the workaround is working.
Can you please explain the cause and clarification?
Best regards,
Kanae
