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Hi, TI teams;
It's our custom board leverage design of TDA4 EVM.
We have confirmed that all power and reset, clock signal we know are at correct states, and
We can successfully connect SOC's M3 core with JTAG. However, when we try to run the initialization script using JTAG, it throws an error at the "write memory" stage.
We checked the DDR0_RESETn signal of LPDDR4, it was driven Low by TDA4.
What may be the cause of the problem that the TDA4 failed to release the reset of DDR? How to check at which stage the boot sequence hangs?
Hi,
Is the DDR part on your custom board different from the one on the EVM?
Regards,
Karan
We solved the problem. we mistakenly connect the bootmode[0]. The latched boot mode is not what we want and prevent further boot steps.