TDA4VM: How to create kernel for QNX？

Hi Guoxun,

When using QNX  the concept of "kernel mode" vs " user mode" is not present.  Please reference the below link for an overview of this - Microkernel architecture (qnx.com).   Additional resources for QNX are available from that link.

Regarding the "illegal instruction", this indicates the QNX process which is running has hit an exception.  Typically this would be due to a memory access to a module that is not clocked or powered, or possibly to an access to a memory address that the running S/W does not have the correct privilege to access.

The ThreadCtl() API can be referred to for increasing / decreasing IO privilege, if the failing access is due to IO privilege.

Regards,

kb

Hi kb,

Is there an example about get access to PMU for QNX? A whole process include power on and ThreadCtl()?

PMU as a coprocessor, does it need special processing?

For "When using QNX  the concept of "kernel mode" vs " user mode" is not present."

Is it means that there is no need to create a kernel for "kernel mode" in QNX system and there is no "kernel mode" for QNX system?

Thanks,

Guoxun

Hi Guoxun,

TI SDK for QNX does not include any A72 PMU based example code.  Some generic links on PMU are below.

• The PMU is an ARM IP module, for which documentation is available online at http://developer.arm.com .   
• The ARM PMU documentation for the A72 is available at: https://developer.arm.com/documentation/100095/0003/performance-monitor-unit
• PMU counters are also referenced in the ARM Architecture Reference Manual ARMv8.

The csl_*Pmu*() functions in  TI SDK for RTOS file, ti-processor-sdk-rtos-j721e-evm-07_02_00_06/pdk_jacinto_07_01_05_14/packages/ti/csl/arch/a53/src/csl_a53.c, can be referenced as a starting point.

Regards, 

kb

Hi kb,

Is PMU of A72 power on by default? 

Now I access to the PMU with instruction msr/mrs(like csl_a53.c): build success, but run failed( Illegal instruction).

The value that get from PMUSERENR_EL0 with the instruction mrs is 0, and the instruction  msr run failed.

Why?

Is the PMU power off by default? How to power on it ?

Hi Guoxun,

In testing on PSDK QNX 7.1, the csl_a53.c, xxCycleCounter APIs when ported to a QNX executable, functioned as expected.  No additional steps were required in terms of clocking and power settings from A72.

For permission to access the PMU registers had to add the below.  

if (ThreadCtl(_NTO_TCTL_IO_PRIV, NULL) == -1) {
  perror("ThreadCtl(_NTO_TCTL_IO_PRIV");
}

Regards,

kb

Hi kb,

Now I can get the cycle count with PMU, but the value is much bigger than expected. Code is as below:

and the result is as below:

Only one add instruction takes 60 cycle counts.(and the cycle counts is different for each execution sometimes.)

Another questions:

When get the value as in the example in  csl_a53.c:

the result is as below:

the value of val (the return value of function getPMUCycleCount()) is different from the value of cycleCount (the get value of function getPMUCycleCount() in main()). Why?

If get the value as below, the value of val is the same as the value of cycleCount :

What's the reason?

Regards,

Guoxun

Hi kb,

I get the overhead about starting/stoping the counter, it's about 60 cycle counts, is this normal?

Guoxun said:

the value of val (the return value of function getPMUCycleCount()) is different from the value of cycleCount (the get value of function getPMUCycleCount() in main()).

What may cause this question? 

Result show:"val is 63", but I get the value with function getPMUCycleCount() is 10(result shows "cycle count is 10").

Regards,

Guoxun