J721EXCPXEVM: How to initialize DDR 4GB in SBL

Seiki Tatesawa

Prodigy 145 points

Part Number: J721EXCPXEVM

Hi,

I would like to initialize DDR(4GB ) in SBL.

・0x00 8000 0000 (2GB) -> SBL has already initialized .

・0x08 8000 0000 (2GB) -> I would like to make SBL to initialize this area.

To do this, is it enough to add another region definition in the following table ?

If SBL can't initialize 4GB DDR, please let us know the constraint( reason ) ?

ti-processor-sdk-rtos-j721e-evm-07_02_00_06\pdk_jacinto_07_01_05_14\packages\ti\boot\sbl\board\k3
sbl_main.c

const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX] =
    ...
    
    {
        /* Region 4 configuration: 2 GB DDR RAM */
        .regionId         = 4U,
        .enable           = 1U,
        .baseAddr         = 0x80000000,
        .size             = CSL_ARM_R5_MPU_REGION_SIZE_2GB,
        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
        .exeNeverControl  = 0U,
        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
        .shareable        = 0U,
        .cacheable        = (uint32_t)TRUE,
        .cachePolicy      = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
        .memAttr          = 0U,
    },

Best Regards,

Seiki Tatesawa

over 4 years ago

0 Karan Saxena over 4 years ago

TI__Guru* 77784 points

Hi Seiki Tatesawa,

The code snippet you have attached is for the MPU (Memory Protection Unit) for the MCU R5F (MCU1_0) where the SBL is running.

MPU is used to program the memory configuration seen by the R5F for the memory it can access. You can read more about MPU in the R5F TRM.

Now R5F being a 32bit processor, it can not access anything beyond the 32bit address range which is 0000_0000 to FFFF_FFFF. (there is RAT which can help access further but to keep the discussion simple I won't bring that here).

DDR is mapped to 0x8000_0000, so essentially a 4GB DDR spans from 0x8000_0000 + 0x1_0000_0000 (4GB) = 0x1_8000_0000

Out of this range, only 0x8000_0000 to 0xFFFF_FFFF which is 2GB can be accessed - hence we only configure this in the MPU.

But that being said, the MPU configuration is only for the R5F, it doesn't have to do anything with DDR initialization. You can map 2GB DDR in the MPU and if the DDR initialization has not been done then the access would still fail.

DDR configuration is done by Board_init(BOARD_INIT_DDR).

Regards,

Karan

0 Seiki Tatesawa over 4 years ago in reply to Karan Saxena

Prodigy 145 points

Hi Karan Saxena

Thank you for your response. I understood the limitation on R5F.

If the RAT can access the 4GB DDR, it possible to initialize 4GB DDR area ?

Or 4GB initialization should be executed on A72 ?

Regards,

Seiki

+1 Karan Saxena over 4 years ago in reply to Seiki Tatesawa

TI__Guru* 77784 points

Hi Seiki,

Are you running some app where you will try to access DDR after the 2GB range? I think the initialization is happening for the whole range but the R5F can access only the 32bit addressable rannge.

Regards,

Karan

0 Seiki Tatesawa over 4 years ago in reply to Karan Saxena

Prodigy 145 points

Hi Karan

Thank you for your reponse.

On A72, I could access the whole range(4GB) of DDR !

Regards,

Seiki

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J721EXCPXEVM: How to initialize DDR 4GB in SBL