TDA4VM: How to optimize boot time on A72

Hi,

The time you measure is with SD boot, correct?

SDK7.2 supports SD boot for Linux and OSPI and eMMC boot are broken due to an architectural change in the SW which when in. These bootmodes are supported as a part of SDK7.3 again.

1. Will it be possible for you to migrate to SDK7.3? Booting from a faster boot media will help your use case finally.

2. Are the timing requirements strictly related to Linux boot to promp or also for remote core firmwares being up?

3. What features are you looking for in Linux? We can trim the DTB to remove modules that are not needed.

Regards,

Karan

Hi Karan,

Time is measured with OSPI boot, SBL/SPL/U-Boot are in OSPI Flash and kernel is in eMMC. For your question,

1. Since our product is going to SOP soon, we will not follow SDK7.3. I think our boot media is correct now.

2. Our application relys on remote cores being up. 

3. Unused peripherals are already deleted in dts.

I think we can get most benefit by optimizing time for A72 communicating with other cores, since it takes really a long time.

Thanks.

Hi Jianhyu huo,

jianyu huo said:

Our application relys on remote cores being up. 

What are all the remote cores that you want to load?

Can you add more details on your end use case?

Best Regards,
Keerthy

Hi Keerthy,

We are making a project of valet parking where DSPs are used for CNN and other CV algorithms, R5Fs are used for networking, camera and some parallel tasks. So applications on A72 relys on them to speed up the calculation.

Thanks.

Hi Jianyu huo,

Can you please send the device tree you are using, preferably a patch on top of the SDK? I was able to use SBL to boot Kernel directly and launch the vision_apps use cases so that would give us some benefit in terms of boot time as we are skipping A72 SPL and A72 u-boot.

I want to use the same stripped down version of the DTB as you, to get some more bump wrt to boot time.

Regards,

Karan

Hi Karan,

Thank you for your information. I'm trying to let SBL boot Kernel directly, and patch of dts is attached. 

Is there any updates on optimizing communications between A72 and other cores?

diff --git a/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index d1a2eb415..006e5040a 100644
--- a/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -17,56 +17,56 @@
 		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
 	};
 
-	gpio_keys: gpio-keys {
-		compatible = "gpio-keys";
-		autorepeat;
-		pinctrl-names = "default";
-		pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>;
-
-		sw10: sw10 {
-			label = "GPIO Key USER1";
-			linux,code = <BTN_0>;
-			gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>;
-		};
-
-		sw11: sw11 {
-			label = "GPIO Key USER2";
-			linux,code = <BTN_1>;
-			gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	evm_12v0: fixedregulator-evm12v0 {
-		/* main supply */
-		compatible = "regulator-fixed";
-		regulator-name = "evm_12v0";
-		regulator-min-microvolt = <12000000>;
-		regulator-max-microvolt = <12000000>;
-		regulator-always-on;
-		regulator-boot-on;
-	};
-
-	vsys_3v3: fixedregulator-vsys3v3 {
-		/* Output of LMS140 */
-		compatible = "regulator-fixed";
-		regulator-name = "vsys_3v3";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		vin-supply = <&evm_12v0>;
-		regulator-always-on;
-		regulator-boot-on;
-	};
-
-	vsys_5v0: fixedregulator-vsys5v0 {
-		/* Output of LM5140 */
-		compatible = "regulator-fixed";
-		regulator-name = "vsys_5v0";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&evm_12v0>;
-		regulator-always-on;
-		regulator-boot-on;
-	};
+	// gpio_keys: gpio-keys {
+	// 	compatible = "gpio-keys";
+	// 	autorepeat;
+	// 	pinctrl-names = "default";
+	// 	pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>;
+
+	// 	sw10: sw10 {
+	// 		label = "GPIO Key USER1";
+	// 		linux,code = <BTN_0>;
+	// 		gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>;
+	// 	};
+
+	// 	sw11: sw11 {
+	// 		label = "GPIO Key USER2";
+	// 		linux,code = <BTN_1>;
+	// 		gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>;
+	// 	};
+	// };
+
+	// evm_12v0: fixedregulator-evm12v0 {
+	// 	/* main supply */
+	// 	compatible = "regulator-fixed";
+	// 	regulator-name = "evm_12v0";
+	// 	regulator-min-microvolt = <12000000>;
+	// 	regulator-max-microvolt = <12000000>;
+	// 	regulator-always-on;
+	// 	regulator-boot-on;
+	// };
+
+	// vsys_3v3: fixedregulator-vsys3v3 {
+	// 	/* Output of LMS140 */
+	// 	compatible = "regulator-fixed";
+	// 	regulator-name = "vsys_3v3";
+	// 	regulator-min-microvolt = <3300000>;
+	// 	regulator-max-microvolt = <3300000>;
+	// 	vin-supply = <&evm_12v0>;
+	// 	regulator-always-on;
+	// 	regulator-boot-on;
+	// };
+
+	// vsys_5v0: fixedregulator-vsys5v0 {
+	// 	/* Output of LM5140 */
+	// 	compatible = "regulator-fixed";
+	// 	regulator-name = "vsys_5v0";
+	// 	regulator-min-microvolt = <5000000>;
+	// 	regulator-max-microvolt = <5000000>;
+	// 	vin-supply = <&evm_12v0>;
+	// 	regulator-always-on;
+	// 	regulator-boot-on;
+	// };
 
 	/* Used for 48KHz family */
 	pll4: pll4_fixed {
@@ -82,49 +82,49 @@
 		clock-frequency = <1083801600>;
 	};
 
-	sound0: sound@0 {
-		compatible = "ti,j721e-cpb-audio";
-		ti,model = "j721e-cpb-analog";
-
-		ti,cpb-mcasp = <&mcasp10>;
-		ti,cpb-codec = <&pcm3168a_1>;
-
-		clocks = <&pll4>, <&pll15>,
-			 <&k3_clks 184 1>,
-			 <&k3_clks 184 2>, <&k3_clks 184 4>,
-			 <&k3_clks 157 371>,
-			 <&k3_clks 157 400>, <&k3_clks 157 401>;
-		clock-names = "pll4", "pll15",
-			      "cpb-mcasp",
-			      "cpb-mcasp-48000", "cpb-mcasp-44100",
-			      "audio-refclk2",
-			      "audio-refclk2-48000", "audio-refclk2-44100";
-	};
-
-	vdd_mmc1: fixedregulator-sd {
-		compatible = "regulator-fixed";
-		regulator-name = "vdd_mmc1";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		enable-active-high;
-		vin-supply = <&vsys_3v3>;
-		gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
-	};
-
-	vdd_sd_dv_alt: gpio-regulator-TLV71033 {
-		compatible = "regulator-gpio";
-		pinctrl-names = "default";
-		pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
-		regulator-name = "tlv71033";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		vin-supply = <&vsys_5v0>;
-		gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>;
-		states = <1800000 0x0
-			  3300000 0x1>;
-	};
+	// sound0: sound@0 {
+	// 	compatible = "ti,j721e-cpb-audio";
+	// 	ti,model = "j721e-cpb-analog";
+
+	// 	ti,cpb-mcasp = <&mcasp10>;
+	// 	ti,cpb-codec = <&pcm3168a_1>;
+
+	// 	clocks = <&pll4>, <&pll15>,
+	// 		 <&k3_clks 184 1>,
+	// 		 <&k3_clks 184 2>, <&k3_clks 184 4>,
+	// 		 <&k3_clks 157 371>,
+	// 		 <&k3_clks 157 400>, <&k3_clks 157 401>;
+	// 	clock-names = "pll4", "pll15",
+	// 		      "cpb-mcasp",
+	// 		      "cpb-mcasp-48000", "cpb-mcasp-44100",
+	// 		      "audio-refclk2",
+	// 		      "audio-refclk2-48000", "audio-refclk2-44100";
+	// };
+
+	// vdd_mmc1: fixedregulator-sd {
+	// 	compatible = "regulator-fixed";
+	// 	regulator-name = "vdd_mmc1";
+	// 	regulator-min-microvolt = <3300000>;
+	// 	regulator-max-microvolt = <3300000>;
+	// 	regulator-boot-on;
+	// 	enable-active-high;
+	// 	vin-supply = <&vsys_3v3>;
+	// 	gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
+	// };
+
+	// vdd_sd_dv_alt: gpio-regulator-TLV71033 {
+	// 	compatible = "regulator-gpio";
+	// 	pinctrl-names = "default";
+	// 	pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
+	// 	regulator-name = "tlv71033";
+	// 	regulator-min-microvolt = <1800000>;
+	// 	regulator-max-microvolt = <3300000>;
+	// 	regulator-boot-on;
+	// 	vin-supply = <&vsys_5v0>;
+	// 	gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>;
+	// 	states = <1800000 0x0
+	// 		  3300000 0x1>;
+	// };
 
 	cpsw9g_virt_mac: main_r5fss_cpsw9g_virt_mac0 {
 		compatible = "ti,j721e-cpsw-virt-mac";
@@ -151,24 +151,28 @@
 		};
 	};
 
-	dp0: connector {
-		compatible = "dp-connector";
-		label = "DP0";
+	// dp0: connector {
+	// 	compatible = "dp-connector";
+	// 	label = "DP0";
 
-		port {
-			dp_connector_in: endpoint {
-				remote-endpoint = <&dp_bridge_output>;
-			};
-		};
+	// 	port {
+	// 		dp_connector_in: endpoint {
+	// 			remote-endpoint = <&dp_bridge_output>;
+	// 		};
+	// 	};
+	// };
+
+	dma_buf_phys {
+		compatible = "ti,dma_buf_phys";
 	};
 };
 
 &main_pmx0 {
-	sw10_button_pins_default: sw10_button_pins_default {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */
-		>;
-	};
+	// sw10_button_pins_default: sw10_button_pins_default {
+	// 	pinctrl-single,pins = <
+	// 		J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */
+	// 	>;
+	// };
 
 	dp0_pins_default: dp0_pins_default {
 		pinctrl-single,pins = <
@@ -176,59 +180,59 @@
 		>;
 	};
 
-	main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */
-		>;
-	};
-
-	main_i2c0_pins_default: main-i2c0-pins-default {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
-			J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
-		>;
-	};
-
-	main_i2c1_pins_default: main-i2c1-pins-default {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
-			J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
-		>;
-	};
-
-	main_i2c3_pins_default: main-i2c3-pins-default {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
-			J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
-		>;
-	};
-
-	main_i2c6_pins_default: main-i2c6-pins-default {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */
-			J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */
-		>;
-	};
-
-	mcasp10_pins_default: mcasp10_pins_default {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */
-			J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */
-			J721E_IOPAD(0x160, PIN_OUTPUT_PULLDOWN, 12) /* (V28) RGMII5_TD3.MCASP10_AXR0 */
-			J721E_IOPAD(0x164, PIN_OUTPUT_PULLDOWN, 12) /* (V29) RGMII5_TD2.MCASP10_AXR1 */
-			J721E_IOPAD(0x170, PIN_OUTPUT_PULLDOWN, 12) /* (U29) RGMII5_TXC.MCASP10_AXR2 */
-			J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 12) /* (U25) RGMII5_RXC.MCASP10_AXR3 */
-			J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 12) /* (V25) RGMII6_TD1.MCASP10_AXR4 */
-			J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 12) /* (W27) RGMII6_TD0.MCASP10_AXR5 */
-			J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 12) /* (W29) RGMII6_TXC.MCASP10_AXR6 */
-		>;
-	};
-
-	audi_ext_refclk2_pins_default: audi_ext_refclk2_pins_default {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */
-		>;
-	};
+	// main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default {
+	// 	pinctrl-single,pins = <
+	// 		J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */
+	// 	>;
+	// };
+
+	// main_i2c0_pins_default: main-i2c0-pins-default {
+	// 	pinctrl-single,pins = <
+	// 		J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
+	// 		J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
+	// 	>;
+	// };
+
+	// main_i2c1_pins_default: main-i2c1-pins-default {
+	// 	pinctrl-single,pins = <
+	// 		J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
+	// 		J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
+	// 	>;
+	// };
+
+	// main_i2c3_pins_default: main-i2c3-pins-default {
+	// 	pinctrl-single,pins = <
+	// 		J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
+	// 		J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
+	// 	>;
+	// };
+
+	// main_i2c6_pins_default: main-i2c6-pins-default {
+	// 	pinctrl-single,pins = <
+	// 		J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */
+	// 		J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */
+	// 	>;
+	// };
+
+	// mcasp10_pins_default: mcasp10_pins_default {
+	// 	pinctrl-single,pins = <
+	// 		J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */
+	// 		J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */
+	// 		J721E_IOPAD(0x160, PIN_OUTPUT_PULLDOWN, 12) /* (V28) RGMII5_TD3.MCASP10_AXR0 */
+	// 		J721E_IOPAD(0x164, PIN_OUTPUT_PULLDOWN, 12) /* (V29) RGMII5_TD2.MCASP10_AXR1 */
+	// 		J721E_IOPAD(0x170, PIN_OUTPUT_PULLDOWN, 12) /* (U29) RGMII5_TXC.MCASP10_AXR2 */
+	// 		J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 12) /* (U25) RGMII5_RXC.MCASP10_AXR3 */
+	// 		J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 12) /* (V25) RGMII6_TD1.MCASP10_AXR4 */
+	// 		J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 12) /* (W27) RGMII6_TD0.MCASP10_AXR5 */
+	// 		J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 12) /* (W29) RGMII6_TXC.MCASP10_AXR6 */
+	// 	>;
+	// };
+
+	// audi_ext_refclk2_pins_default: audi_ext_refclk2_pins_default {
+	// 	pinctrl-single,pins = <
+	// 		J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */
+	// 	>;
+	// };
 
 	main_mmc1_pins_default: main_mmc1_pins_default {
 		pinctrl-single,pins = <
@@ -244,45 +248,45 @@
 		>;
 	};
 
-	vdd_sd_dv_alt_pins_default: vdd_sd_dv_alt_pins_default {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */
-		>;
-	};
+	// vdd_sd_dv_alt_pins_default: vdd_sd_dv_alt_pins_default {
+	// 	pinctrl-single,pins = <
+	// 		J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */
+	// 	>;
+	// };
 
-	main_usbss0_pins_default: main_usbss0_pins_default {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
-			J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
-		>;
-	};
+	// main_usbss0_pins_default: main_usbss0_pins_default {
+	// 	pinctrl-single,pins = <
+	// 		J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
+	// 		J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
+	// 	>;
+	// };
 
-	main_usbss1_pins_default: main_usbss1_pins_default {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
-		>;
-	};
+	// main_usbss1_pins_default: main_usbss1_pins_default {
+	// 	pinctrl-single,pins = <
+	// 		J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
+	// 	>;
+	// };
 };
 
 &wkup_pmx0 {
-	sw11_button_pins_default: sw11_button_pins_default {
-		pinctrl-single,pins = <
-			J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */
-		>;
-	};
-
-	mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
-		pinctrl-single,pins = <
-			J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */
-			J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */
-			J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */
-			J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */
-			J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */
-			J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */
-			J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */
-			J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */
-		>;
-	};
+	// sw11_button_pins_default: sw11_button_pins_default {
+	// 	pinctrl-single,pins = <
+	// 		J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */
+	// 	>;
+	// };
+
+	// mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
+	// 	pinctrl-single,pins = <
+	// 		J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */
+	// 		J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */
+	// 		J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */
+	// 		J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */
+	// 		J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */
+	// 		J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */
+	// 		J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */
+	// 		J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */
+	// 	>;
+	// };
 };
 
 &wkup_pmx0 {
@@ -310,100 +314,100 @@
 		>;
 	};
 
-	mcu_mcan0_pins_default: mcu-mcan0-pins-default {
-		pinctrl-single,pins = <
-			J721E_WKUP_IOPAD(0xac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */
-			J721E_WKUP_IOPAD(0xa8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */
-		>;
-	};
-
-	mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default {
-		pinctrl-single,pins = <
-			J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* (F26) WKUP_GPIO0_0 */
-			J721E_WKUP_IOPAD(0x98, PIN_INPUT, 7) /* (E28) MCU_SPI0_D1.WKUP_GPIO0_54 */
-		>;
-	};
-
-	mcu_mcan1_pins_default: mcu-mcan1-pins-default {
-		pinctrl-single,pins = <
-			J721E_WKUP_IOPAD(0xc4, PIN_INPUT, 0) /* (G24) WKUP_GPIO0_5.MCU_MCAN1_RX */
-			J721E_WKUP_IOPAD(0xc0, PIN_OUTPUT, 0) /* (G25) WKUP_GPIO0_4.MCU_MCAN1_TX */
-		>;
-	};
-
-	mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default {
-		pinctrl-single,pins = <
-			J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* (F28) WKUP_GPIO0_2 */
-		>;
-	};
-};
-
-&wkup_uart0 {
-	/* Wakeup UART is used by System firmware */
-	status = "disabled";
-};
-
-&main_uart0 {
-	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
-};
-
-&main_uart3 {
-	/* UART not brought out */
-	status = "disabled";
-};
-
-&main_uart5 {
-	/* UART not brought out */
-	status = "disabled";
-};
-
-&main_uart6 {
-	/* UART not brought out */
-	status = "disabled";
-};
-
-&main_uart7 {
-	/* UART not brought out */
-	status = "disabled";
-};
-
-&main_uart8 {
-	/* UART not brought out */
-	status = "disabled";
-};
-
-&main_uart9 {
-	/* UART not brought out */
-	status = "disabled";
-};
-
-&main_gpio2 {
-	status = "disabled";
-};
-
-&main_gpio3 {
-	status = "disabled";
-};
-
-&main_gpio4 {
-	status = "disabled";
-};
-
-&main_gpio5 {
-	status = "disabled";
-};
-
-&main_gpio6 {
-	status = "disabled";
-};
-
-&main_gpio7 {
-	status = "disabled";
-};
-
-&wkup_gpio1 {
-	status = "disabled";
-};
+	// mcu_mcan0_pins_default: mcu-mcan0-pins-default {
+	// 	pinctrl-single,pins = <
+	// 		J721E_WKUP_IOPAD(0xac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */
+	// 		J721E_WKUP_IOPAD(0xa8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */
+	// 	>;
+	// };
+
+	// mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default {
+	// 	pinctrl-single,pins = <
+	// 		J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* (F26) WKUP_GPIO0_0 */
+	// 		J721E_WKUP_IOPAD(0x98, PIN_INPUT, 7) /* (E28) MCU_SPI0_D1.WKUP_GPIO0_54 */
+	// 	>;
+	// };
+
+	// mcu_mcan1_pins_default: mcu-mcan1-pins-default {
+	// 	pinctrl-single,pins = <
+	// 		J721E_WKUP_IOPAD(0xc4, PIN_INPUT, 0) /* (G24) WKUP_GPIO0_5.MCU_MCAN1_RX */
+	// 		J721E_WKUP_IOPAD(0xc0, PIN_OUTPUT, 0) /* (G25) WKUP_GPIO0_4.MCU_MCAN1_TX */
+	// 	>;
+	// };
+
+	// mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default {
+	// 	pinctrl-single,pins = <
+	// 		J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* (F28) WKUP_GPIO0_2 */
+	// 	>;
+	// };
+};
+
+// &wkup_uart0 {
+// 	/* Wakeup UART is used by System firmware */
+// 	status = "disabled";
+// };
+
+// &main_uart0 {
+// 	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
+// };
+
+// &main_uart3 {
+// 	/* UART not brought out */
+// 	status = "disabled";
+// };
+
+// &main_uart5 {
+// 	/* UART not brought out */
+// 	status = "disabled";
+// };
+
+// &main_uart6 {
+// 	/* UART not brought out */
+// 	status = "disabled";
+// };
+
+// &main_uart7 {
+// 	/* UART not brought out */
+// 	status = "disabled";
+// };
+
+// &main_uart8 {
+// 	/* UART not brought out */
+// 	status = "disabled";
+// };
+
+// &main_uart9 {
+// 	/* UART not brought out */
+// 	status = "disabled";
+// };
+
+// &main_gpio2 {
+// 	status = "disabled";
+// };
+
+// &main_gpio3 {
+// 	status = "disabled";
+// };
+
+// &main_gpio4 {
+// 	status = "disabled";
+// };
+
+// &main_gpio5 {
+// 	status = "disabled";
+// };
+
+// &main_gpio6 {
+// 	status = "disabled";
+// };
+
+// &main_gpio7 {
+// 	status = "disabled";
+// };
+
+// &wkup_gpio1 {
+// 	status = "disabled";
+// };
 
 &mailbox0_cluster0 {
 	interrupts = <436>;
@@ -534,237 +538,238 @@
 	mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
 };
 
-&ospi1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
-
-	flash@0{
-		compatible = "jedec,spi-nor";
-		reg = <0x0>;
-		spi-tx-bus-width = <1>;
-		spi-rx-bus-width = <4>;
-		spi-max-frequency = <40000000>;
-		cdns,tshsl-ns = <60>;
-		cdns,tsd2d-ns = <60>;
-		cdns,tchsh-ns = <60>;
-		cdns,tslch-ns = <60>;
-		cdns,read-delay = <2>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-	};
-};
-
-&tscadc0 {
-	adc {
-		ti,adc-channels = <0 1 2 3 4 5 6 7>;
-	};
-};
-
-&tscadc1 {
-	adc {
-		ti,adc-channels = <0 1 2 3 4 5 6 7>;
-	};
-};
-
-&dss {
-	status = "ok";
-};
-
-&dss_ports {
-	#address-cells = <1>;
-	#size-cells = <0>;
-
-	port@0 {
-		reg = <0>;
-
-		dpi_out_real0: endpoint {
-			remote-endpoint = <&dp_bridge_input>;
-		};
-	};
-};
-
-&mhdp {
-	status = "ok";
-	pinctrl-names = "default";
-	pinctrl-0 = <&dp0_pins_default>;
-};
-
-&dp0_ports {
-	#address-cells = <1>;
-	#size-cells = <0>;
-
-	port@0 {
-		reg = <0>;
-		dp_bridge_input: endpoint {
-			remote-endpoint = <&dpi_out_real0>;
-		};
-	};
-
-	port@1 {
-		reg = <1>;
-		dp_bridge_output: endpoint {
-			remote-endpoint = <&dp_connector_in>;
-		};
-	};
-};
-
-&main_i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_i2c0_pins_default>;
-	clock-frequency = <400000>;
-
-	exp1: gpio@20 {
-		compatible = "ti,tca6416";
-		reg = <0x20>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
-
-	exp2: gpio@22 {
-		compatible = "ti,tca6424";
-		reg = <0x22>;
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		p09 {
-			/* P11 - MCASP/TRACE_MUX_S0 */
-			gpio-hog;
-			gpios = <9 GPIO_ACTIVE_HIGH>;
-			output-low;
-			line-name = "MCASP/TRACE_MUX_S0";
-		};
-
-		p10 {
-			/* P12 - MCASP/TRACE_MUX_S1 */
-			gpio-hog;
-			gpios = <10 GPIO_ACTIVE_HIGH>;
-			output-high;
-			line-name = "MCASP/TRACE_MUX_S1";
-		};
-	};
-};
-
-&main_i2c1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_i2c1_pins_default>;
-	clock-frequency = <400000>;
-
-	exp4: gpio@20 {
-		compatible = "ti,tca6408";
-		reg = <0x20>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&main_i2c1_exp4_pins_default>;
-		interrupt-parent = <&main_gpio1>;
-		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-
-		p0 {
-			/* P0 - DP0_PWR_SW_EN */
-			gpio-hog;
-			gpios = <0 GPIO_ACTIVE_HIGH>;
-			output-high;
-			line-name = "DP0_PWR_SW_EN";
-		};
-	};
-};
-
-&k3_clks {
-	/* Confiure AUDIO_EXT_REFCLK2 pin as output */
-	pinctrl-names = "default";
-	pinctrl-0 = <&audi_ext_refclk2_pins_default>;
-};
-
-&main_i2c3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_i2c3_pins_default>;
-	clock-frequency = <400000>;
-
-	exp3: gpio@20 {
-		compatible = "ti,tca6408";
-		reg = <0x20>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
-
-	pcm3168a_1: audio-codec@44 {
-		compatible = "ti,pcm3168a";
-		reg = <0x44>;
-
-		#sound-dai-cells = <1>;
-
-		reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>;
-
-		/* C_AUDIO_REFCLK2 -> RGMII6_RXC (W26) */
-		clocks = <&k3_clks 157 371>;
-		clock-names = "scki";
-
-		/* HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK -> REFCLK2 */
-		assigned-clocks = <&k3_clks 157 371>;
-		assigned-clock-parents = <&k3_clks 157 400>;
-		assigned-clock-rates = <24576000>; /* for 48KHz */
-
-		VDD1-supply = <&vsys_3v3>;
-		VDD2-supply = <&vsys_3v3>;
-		VCCAD1-supply = <&vsys_5v0>;
-		VCCAD2-supply = <&vsys_5v0>;
-		VCCDA1-supply = <&vsys_5v0>;
-		VCCDA2-supply = <&vsys_5v0>;
-	};
-};
-
-&main_i2c6 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_i2c6_pins_default>;
-	clock-frequency = <400000>;
-
-	exp5: gpio@20 {
-		compatible = "ti,tca6408";
-		reg = <0x20>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
-};
-
-&mcasp10 {
-	#sound-dai-cells = <0>;
-
-	pinctrl-names = "default";
-	pinctrl-0 = <&mcasp10_pins_default>;
-
-	op-mode = <0>;          /* MCASP_IIS_MODE */
-	tdm-slots = <2>;
-	auxclk-fs-ratio = <256>;
-
-	serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
-		1 1 1 1
-		2 2 2 0
-	>;
-	tx-num-evt = <0>;
-	rx-num-evt = <0>;
-
-	status = "okay";
-};
-
-&mcu_cpsw {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
-};
-
-&davinci_mdio {
-	phy0: ethernet-phy@0 {
-		reg = <0>;
-		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
-		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
-	};
-};
-
-&cpsw_port1 {
-	phy-mode = "rgmii-rxid";
-	phy-handle = <&phy0>;
-};
+// &ospi1 {
+// 	pinctrl-names = "default";
+// 	pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
+
+// 	flash@0{
+// 		compatible = "jedec,spi-nor";
+// 		reg = <0x0>;
+// 		spi-tx-bus-width = <1>;
+// 		spi-rx-bus-width = <4>;
+// 		spi-max-frequency = <40000000>;
+// 		cdns,tshsl-ns = <60>;
+// 		cdns,tsd2d-ns = <60>;
+// 		cdns,tchsh-ns = <60>;
+// 		cdns,tslch-ns = <60>;
+// 		cdns,read-delay = <2>;
+// 		#address-cells = <1>;
+// 		#size-cells = <1>;
+// 	};
+// };
+
+// &tscadc0 {
+// 	adc {
+// 		ti,adc-channels = <0 1 2 3 4 5 6 7>;
+// 	};
+// };
+
+// &tscadc1 {
+// 	adc {
+// 		ti,adc-channels = <0 1 2 3 4 5 6 7>;
+// 	};
+// };
+
+// &dss {
+// 	status = "ok";
+// };
+
+// &dss_ports {
+// 	#address-cells = <1>;
+// 	#size-cells = <0>;
+
+// 	port@0 {
+// 		reg = <0>;
+
+// 		dpi_out_real0: endpoint {
+// 			remote-endpoint = <&dp_bridge_input>;
+// 		};
+// 	};
+// };
+
+// &mhdp {
+// 	status = "ok";
+// 	pinctrl-names = "default";
+// 	pinctrl-0 = <&dp0_pins_default>;
+// };
+
+// &dp0_ports {
+// 	#address-cells = <1>;
+// 	#size-cells = <0>;
+
+// 	port@0 {
+// 		reg = <0>;
+// 		dp_bridge_input: endpoint {
+// 			remote-endpoint = <&dpi_out_real0>;
+// 		};
+// 	};
+
+// 	port@1 {
+// 		reg = <1>;
+// 		dp_bridge_output: endpoint {
+// 			remote-endpoint = <&dp_connector_in>;
+// 		};
+// 	};
+// };
+
+// &main_i2c0 {
+// 	pinctrl-names = "default";
+// 	pinctrl-0 = <&main_i2c0_pins_default>;
+// 	clock-frequency = <400000>;
+
+// 	exp1: gpio@20 {
+// 		compatible = "ti,tca6416";
+// 		reg = <0x20>;
+// 		gpio-controller;
+// 		#gpio-cells = <2>;
+// 	};
+
+// 	exp2: gpio@22 {
+// 		compatible = "ti,tca6424";
+// 		reg = <0x22>;
+// 		gpio-controller;
+// 		#gpio-cells = <2>;
+
+// 		p09 {
+// 			/* P11 - MCASP/TRACE_MUX_S0 */
+// 			gpio-hog;
+// 			gpios = <9 GPIO_ACTIVE_HIGH>;
+// 			output-low;
+// 			line-name = "MCASP/TRACE_MUX_S0";
+// 		};
+
+// 		p10 {
+// 			/* P12 - MCASP/TRACE_MUX_S1 */
+// 			gpio-hog;
+// 			gpios = <10 GPIO_ACTIVE_HIGH>;
+// 			output-high;
+// 			line-name = "MCASP/TRACE_MUX_S1";
+// 		};
+// 	};
+// };
+
+// &main_i2c1 {
+// 	pinctrl-names = "default";
+// 	pinctrl-0 = <&main_i2c1_pins_default>;
+// 	clock-frequency = <400000>;
+
+// 	exp4: gpio@20 {
+// 		compatible = "ti,tca6408";
+// 		reg = <0x20>;
+// 		gpio-controller;
+// 		#gpio-cells = <2>;
+// 		pinctrl-names = "default";
+// 		pinctrl-0 = <&main_i2c1_exp4_pins_default>;
+// 		interrupt-parent = <&main_gpio1>;
+// 		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+// 		interrupt-controller;
+// 		#interrupt-cells = <2>;
+
+// 		p0 {
+// 			/* P0 - DP0_PWR_SW_EN */
+// 			gpio-hog;
+// 			gpios = <0 GPIO_ACTIVE_HIGH>;
+// 			output-high;
+// 			line-name = "DP0_PWR_SW_EN";
+// 		};
+// 	};
+// };
+
+// &k3_clks {
+// 	/* Confiure AUDIO_EXT_REFCLK2 pin as output */
+// 	pinctrl-names = "default";
+// 	pinctrl-0 = <&audi_ext_refclk2_pins_default>;
+// };
+
+// &main_i2c3 {
+// 	pinctrl-names = "default";
+// 	pinctrl-0 = <&main_i2c3_pins_default>;
+// 	clock-frequency = <400000>;
+
+// 	exp3: gpio@20 {
+// 		compatible = "ti,tca6408";
+// 		reg = <0x20>;
+// 		gpio-controller;
+// 		#gpio-cells = <2>;
+// 	};
+
+// 	pcm3168a_1: audio-codec@44 {
+// 		compatible = "ti,pcm3168a";
+// 		reg = <0x44>;
+
+// 		#sound-dai-cells = <1>;
+
+// 		reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>;
+
+// 		/* C_AUDIO_REFCLK2 -> RGMII6_RXC (W26) */
+// 		clocks = <&k3_clks 157 371>;
+// 		clock-names = "scki";
+
+// 		/* HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK -> REFCLK2 */
+// 		assigned-clocks = <&k3_clks 157 371>;
+// 		assigned-clock-parents = <&k3_clks 157 400>;
+// 		assigned-clock-rates = <24576000>; /* for 48KHz */
+
+// 		VDD1-supply = <&vsys_3v3>;
+// 		VDD2-supply = <&vsys_3v3>;
+// 		VCCAD1-supply = <&vsys_5v0>;
+// 		VCCAD2-supply = <&vsys_5v0>;
+// 		VCCDA1-supply = <&vsys_5v0>;
+// 		VCCDA2-supply = <&vsys_5v0>;
+// 	};
+// };
+
+// &main_i2c6 {
+// 	pinctrl-names = "default";
+// 	pinctrl-0 = <&main_i2c6_pins_default>;
+// 	clock-frequency = <400000>;
+
+// 	exp5: gpio@20 {
+// 		compatible = "ti,tca6408";
+// 		reg = <0x20>;
+// 		gpio-controller;
+// 		#gpio-cells = <2>;
+// 	};
+// };
+
+// &mcasp10 {
+// 	#sound-dai-cells = <0>;
+
+// 	pinctrl-names = "default";
+// 	pinctrl-0 = <&mcasp10_pins_default>;
+
+// 	op-mode = <0>;          /* MCASP_IIS_MODE */
+// 	tdm-slots = <2>;
+// 	auxclk-fs-ratio = <256>;
+
+// 	serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
+// 		1 1 1 1
+// 		2 2 2 0
+// 	>;
+// 	tx-num-evt = <0>;
+// 	rx-num-evt = <0>;
+
+// 	status = "okay";
+// };
+
+// &mcu_cpsw {
+// 	pinctrl-names = "default";
+// 	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+// };
+
+// &davinci_mdio {
+// 	phy0: ethernet-phy@3 {
+// 		reg = <3>;
+// 		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+// 		ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+// 		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+// 	};
+// };
+
+// &cpsw_port1 {
+// 	phy-mode = "rgmii-rxid";
+// 	phy-handle = <&phy0>;
+// };
 
 &main_sdhci0 {
 	/* eMMC */
@@ -775,227 +780,227 @@
 
 &main_sdhci1 {
 	/* SD/MMC */
-	vmmc-supply = <&vdd_mmc1>;
-	vqmmc-supply = <&vdd_sd_dv_alt>;
+	// vmmc-supply = <&vdd_mmc1>;
+	// vqmmc-supply = <&vdd_sd_dv_alt>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&main_mmc1_pins_default>;
 	disable-wp;
 };
 
-&main_sdhci2 {
-	/* Unused */
-	status = "disabled";
-};
-
-&serdes0 {
-	serdes0_pcie_link: link@0 {
-		reg = <0>;
-		cdns,num-lanes = <1>;
-		#phy-cells = <0>;
-		cdns,phy-type = <PHY_TYPE_PCIE>;
-		resets = <&serdes_wiz0 1>;
-	};
-};
-
-&serdes1 {
-	serdes1_pcie_link: link@0 {
-		reg = <0>;
-		cdns,num-lanes = <2>;
-		#phy-cells = <0>;
-		cdns,phy-type = <PHY_TYPE_PCIE>;
-		resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
-	};
-};
-
-&serdes2 {
-	serdes2_pcie_link: link@0 {
-		reg = <0>;
-		cdns,num-lanes = <2>;
-		#phy-cells = <0>;
-		cdns,phy-type = <PHY_TYPE_PCIE>;
-		resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>;
-	};
-};
-
-&pcie0_rc {
-	reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
-	phys = <&serdes0_pcie_link>;
-	phy-names = "pcie_phy";
-	num-lanes = <1>;
-};
-
-&pcie1_rc {
-	reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
-	phys = <&serdes1_pcie_link>;
-	phy-names = "pcie_phy";
-	num-lanes = <2>;
-};
-
-&pcie2_rc {
-	reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>;
-	phys = <&serdes2_pcie_link>;
-	phy-names = "pcie_phy";
-	num-lanes = <2>;
-};
-
-&pcie0_ep {
-	phys = <&serdes0_pcie_link>;
-	phy-names = "pcie_phy";
-	num-lanes = <1>;
-	status = "disabled";
-};
-
-&pcie1_ep {
-	phys = <&serdes1_pcie_link>;
-	phy-names = "pcie_phy";
-	num-lanes = <2>;
-	status = "disabled";
-};
-
-&pcie2_ep {
-	phys = <&serdes2_pcie_link>;
-	phy-names = "pcie_phy";
-	num-lanes = <2>;
-	status = "disabled";
-};
-
-&pcie3_rc {
-	status = "disabled";
-};
-
-&pcie3_ep {
-	status = "disabled";
-};
-
-&usb_serdes_mux {
-	idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */
-};
-
-&serdes_ln_ctrl {
-	idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
-		      <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
-		      <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
-		      <SERDES3_LANE0_USB3_0_SWAP>, <SERDES3_LANE1_USB3_0>,
-		      <SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
-};
-
-&serdes_wiz3 {
-	typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
-	typec-dir-debounce-ms = <700>;	/* TUSB321, tCCB_DEFAULT 133 ms */
-};
-
-&serdes3 {
-	serdes3_usb_link: link@0 {
-		reg = <0>;
-		cdns,num-lanes = <2>;
-		#phy-cells = <0>;
-		cdns,phy-type = <PHY_TYPE_USB3>;
-		resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
-	};
-};
-
-&usbss0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_usbss0_pins_default>;
-	ti,vbus-divider;
-};
-
-&usb0 {
-	dr_mode = "otg";
-	maximum-speed = "super-speed";
-	phys = <&serdes3_usb_link>;
-	phy-names = "cdns3,usb3-phy";
-};
-
-&usbss1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_usbss1_pins_default>;
-	ti,usb2-only;
-};
-
-&usb1 {
-	dr_mode = "host";
-	maximum-speed = "high-speed";
-};
-
-/* uart2 assigned to cpsw9g eth-switch fw running on remote CPU core */
-&main_uart2 {
-	status = "disabled";
-};
-
-&mcu_mcan0 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&mcu_mcan0_pins_default &mcu_mcan0_gpio_pins_default>;
-	stb-gpios = <&wkup_gpio0 54 GPIO_ACTIVE_HIGH>;
-	en-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>;
-	can-transceiver {
-		max-bitrate = <5000000>;
-	};
-};
-
-&mcu_mcan1 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&mcu_mcan1_pins_default &mcu_mcan1_gpio_pins_default>;
-	stb-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_LOW>;
-	can-transceiver {
-		max-bitrate = <5000000>;
-	};
-};
-
-&main_mcan0 {
-	status = "disabled";
-};
-
-&main_mcan1 {
-	status = "disabled";
-};
-
-&main_mcan2 {
-	status = "disabled";
-};
-
-&main_mcan3 {
-	status = "disabled";
-};
-
-&main_mcan4 {
-	status = "disabled";
-};
-
-&main_mcan5 {
-	status = "disabled";
-};
-
-&main_mcan6 {
-	status = "disabled";
-};
-
-&main_mcan7 {
-	status = "disabled";
-};
-
-&main_mcan8 {
-	status = "disabled";
-};
-
-&main_mcan9 {
-	status = "disabled";
-};
-
-&main_mcan10 {
-	status = "disabled";
-};
-
-&main_mcan11 {
-	status = "disabled";
-};
-
-&main_mcan12 {
-	status = "disabled";
-};
-
-&main_mcan13 {
-	status = "disabled";
-};
+// &main_sdhci2 {
+// 	/* Unused */
+// 	status = "disabled";
+// };
+
+// &serdes0 {
+// 	serdes0_pcie_link: link@0 {
+// 		reg = <0>;
+// 		cdns,num-lanes = <1>;
+// 		#phy-cells = <0>;
+// 		cdns,phy-type = <PHY_TYPE_PCIE>;
+// 		resets = <&serdes_wiz0 1>;
+// 	};
+// };
+
+// &serdes1 {
+// 	serdes1_pcie_link: link@0 {
+// 		reg = <0>;
+// 		cdns,num-lanes = <2>;
+// 		#phy-cells = <0>;
+// 		cdns,phy-type = <PHY_TYPE_PCIE>;
+// 		resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
+// 	};
+// };
+
+// &serdes2 {
+// 	serdes2_pcie_link: link@0 {
+// 		reg = <0>;
+// 		cdns,num-lanes = <2>;
+// 		#phy-cells = <0>;
+// 		cdns,phy-type = <PHY_TYPE_PCIE>;
+// 		resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>;
+// 	};
+// };
+
+// &pcie0_rc {
+// 	reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
+// 	phys = <&serdes0_pcie_link>;
+// 	phy-names = "pcie_phy";
+// 	num-lanes = <1>;
+// };
+
+// &pcie1_rc {
+// 	reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
+// 	phys = <&serdes1_pcie_link>;
+// 	phy-names = "pcie_phy";
+// 	num-lanes = <2>;
+// };
+
+// &pcie2_rc {
+// 	reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>;
+// 	phys = <&serdes2_pcie_link>;
+// 	phy-names = "pcie_phy";
+// 	num-lanes = <2>;
+// };
+
+// &pcie0_ep {
+// 	phys = <&serdes0_pcie_link>;
+// 	phy-names = "pcie_phy";
+// 	num-lanes = <1>;
+// 	status = "disabled";
+// };
+
+// &pcie1_ep {
+// 	phys = <&serdes1_pcie_link>;
+// 	phy-names = "pcie_phy";
+// 	num-lanes = <2>;
+// 	status = "disabled";
+// };
+
+// &pcie2_ep {
+// 	phys = <&serdes2_pcie_link>;
+// 	phy-names = "pcie_phy";
+// 	num-lanes = <2>;
+// 	status = "disabled";
+// };
+
+// &pcie3_rc {
+// 	status = "disabled";
+// };
+
+// &pcie3_ep {
+// 	status = "disabled";
+// };
+
+// &usb_serdes_mux {
+// 	idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */
+// };
+
+// &serdes_ln_ctrl {
+// 	idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
+// 		      <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
+// 		      <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
+// 		      <SERDES3_LANE0_USB3_0_SWAP>, <SERDES3_LANE1_USB3_0>,
+// 		      <SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
+// };
+
+// &serdes_wiz3 {
+// 	typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
+// 	typec-dir-debounce-ms = <700>;	/* TUSB321, tCCB_DEFAULT 133 ms */
+// };
+
+// &serdes3 {
+// 	serdes3_usb_link: link@0 {
+// 		reg = <0>;
+// 		cdns,num-lanes = <2>;
+// 		#phy-cells = <0>;
+// 		cdns,phy-type = <PHY_TYPE_USB3>;
+// 		resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
+// 	};
+// };
+
+// &usbss0 {
+// 	pinctrl-names = "default";
+// 	pinctrl-0 = <&main_usbss0_pins_default>;
+// 	ti,vbus-divider;
+// };
+
+// &usb0 {
+// 	dr_mode = "otg";
+// 	maximum-speed = "super-speed";
+// 	phys = <&serdes3_usb_link>;
+// 	phy-names = "cdns3,usb3-phy";
+// };
+
+// &usbss1 {
+// 	pinctrl-names = "default";
+// 	pinctrl-0 = <&main_usbss1_pins_default>;
+// 	ti,usb2-only;
+// };
+
+// &usb1 {
+// 	dr_mode = "host";
+// 	maximum-speed = "high-speed";
+// };
+
+// /* uart2 assigned to cpsw9g eth-switch fw running on remote CPU core */
+// &main_uart2 {
+// 	status = "disabled";
+// };
+
+// &mcu_mcan0 {
+// 	status = "okay";
+// 	pinctrl-names = "default";
+// 	pinctrl-0 = <&mcu_mcan0_pins_default &mcu_mcan0_gpio_pins_default>;
+// 	stb-gpios = <&wkup_gpio0 54 GPIO_ACTIVE_HIGH>;
+// 	en-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>;
+// 	can-transceiver {
+// 		max-bitrate = <5000000>;
+// 	};
+// };
+
+// &mcu_mcan1 {
+// 	status = "okay";
+// 	pinctrl-names = "default";
+// 	pinctrl-0 = <&mcu_mcan1_pins_default &mcu_mcan1_gpio_pins_default>;
+// 	stb-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_LOW>;
+// 	can-transceiver {
+// 		max-bitrate = <5000000>;
+// 	};
+// };
+
+// &main_mcan0 {
+// 	status = "disabled";
+// };
+
+// &main_mcan1 {
+// 	status = "disabled";
+// };
+
+// &main_mcan2 {
+// 	status = "disabled";
+// };
+
+// &main_mcan3 {
+// 	status = "disabled";
+// };
+
+// &main_mcan4 {
+// 	status = "disabled";
+// };
+
+// &main_mcan5 {
+// 	status = "disabled";
+// };
+
+// &main_mcan6 {
+// 	status = "disabled";
+// };
+
+// &main_mcan7 {
+// 	status = "disabled";
+// };
+
+// &main_mcan8 {
+// 	status = "disabled";
+// };
+
+// &main_mcan9 {
+// 	status = "disabled";
+// };
+
+// &main_mcan10 {
+// 	status = "disabled";
+// };
+
+// &main_mcan11 {
+// 	status = "disabled";
+// };
+
+// &main_mcan12 {
+// 	status = "disabled";
+// };
+
+// &main_mcan13 {
+// 	status = "disabled";
+// };
\ No newline at end of file
diff --git a/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 8675a4887..ece26934a 100644
--- a/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -23,56 +23,56 @@
 		};
 	};
 
-	scm_conf: scm_conf@100000 {
-		compatible = "syscon", "simple-mfd";
-		reg = <0 0x00100000 0 0x1c000>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x0 0x0 0x00100000 0x1c000>;
-
-		pcie0_ctrl: pcie-ctrl@4070 {
-			compatible = "syscon";
-			reg = <0x00004070 0x4>;
-		};
-
-		pcie1_ctrl: pcie-ctrl@4074 {
-			compatible = "syscon";
-			reg = <0x00004074 0x4>;
-		};
-
-		pcie2_ctrl: pcie-ctrl@4078 {
-			compatible = "syscon";
-			reg = <0x00004078 0x4>;
-		};
-
-		pcie3_ctrl: pcie-ctrl@407c {
-			compatible = "syscon";
-			reg = <0x0000407c 0x4>;
-		};
-
-		serdes_ln_ctrl: serdes_ln_ctrl@4080 {
-			compatible = "mmio-mux";
-			#mux-control-cells = <1>;
-			mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
-					<0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
-					<0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
-					<0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
-					<0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
-					/* SERDES4 lane0/1/2/3 select */
-			idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
-				      <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
-				      <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
-				      <MUX_IDLE_AS_IS>, <SERDES3_LANE1_USB3_0>,
-				      <SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
-		};
-
-		usb_serdes_mux: mux-controller@4000 {
-			compatible = "mmio-mux";
-			#mux-control-cells = <1>;
-			mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
-					<0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */
-	    };
-	};
+	// scm_conf: scm_conf@100000 {
+	// 	compatible = "syscon", "simple-mfd";
+	// 	reg = <0 0x00100000 0 0x1c000>;
+	// 	#address-cells = <1>;
+	// 	#size-cells = <1>;
+	// 	ranges = <0x0 0x0 0x00100000 0x1c000>;
+
+	// 	pcie0_ctrl: pcie-ctrl@4070 {
+	// 		compatible = "syscon";
+	// 		reg = <0x00004070 0x4>;
+	// 	};
+
+	// 	pcie1_ctrl: pcie-ctrl@4074 {
+	// 		compatible = "syscon";
+	// 		reg = <0x00004074 0x4>;
+	// 	};
+
+	// 	pcie2_ctrl: pcie-ctrl@4078 {
+	// 		compatible = "syscon";
+	// 		reg = <0x00004078 0x4>;
+	// 	};
+
+	// 	pcie3_ctrl: pcie-ctrl@407c {
+	// 		compatible = "syscon";
+	// 		reg = <0x0000407c 0x4>;
+	// 	};
+
+	// 	serdes_ln_ctrl: serdes_ln_ctrl@4080 {
+	// 		compatible = "mmio-mux";
+	// 		#mux-control-cells = <1>;
+	// 		mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
+	// 				<0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
+	// 				<0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
+	// 				<0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
+	// 				<0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
+	// 				/* SERDES4 lane0/1/2/3 select */
+	// 		idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
+	// 			      <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
+	// 			      <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
+	// 			      <MUX_IDLE_AS_IS>, <SERDES3_LANE1_USB3_0>,
+	// 			      <SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
+	// 	};
+
+	// 	usb_serdes_mux: mux-controller@4000 {
+	// 		compatible = "mmio-mux";
+	// 		#mux-control-cells = <1>;
+	// 		mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
+	// 				<0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */
+	//     };
+	// };
 
 	gic500: interrupt-controller@1800000 {
 		compatible = "arm,gic-v3";
@@ -96,16 +96,16 @@
 		};
 	};
 
-	main_gpio_intr: interrupt-controller0 {
-		compatible = "ti,sci-intr";
-		ti,intr-trigger-type = <1>;
-		interrupt-controller;
-		interrupt-parent = <&gic500>;
-		#interrupt-cells = <1>;
-		ti,sci = <&dmsc>;
-		ti,sci-dev-id = <131>;
-		ti,interrupt-ranges = <8 392 56>;
-	};
+	// main_gpio_intr: interrupt-controller0 {
+	// 	compatible = "ti,sci-intr";
+	// 	ti,intr-trigger-type = <1>;
+	// 	interrupt-controller;
+	// 	interrupt-parent = <&gic500>;
+	// 	#interrupt-cells = <1>;
+	// 	ti,sci = <&dmsc>;
+	// 	ti,sci-dev-id = <131>;
+	// 	ti,interrupt-ranges = <8 392 56>;
+	// };
 
 	cbass_main_navss: navss@30000000 {
 		compatible = "simple-mfd";
@@ -421,567 +421,567 @@
 		clock-frequency = <0>;
 	};
 
-	serdes_wiz0: wiz@5000000 {
-		compatible = "ti,j721e-wiz-16g";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
-		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
-		assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
-		assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
-		num-lanes = <2>;
-		#reset-cells = <1>;
-		ranges = <0x5000000 0x0 0x5000000 0x10000>;
-
-		wiz0_pll0_refclk: pll0-refclk {
-			clocks = <&k3_clks 292 11>, <&dummy_cmn_refclk>;
-			#clock-cells = <0>;
-			assigned-clocks = <&wiz0_pll0_refclk>;
-			assigned-clock-parents = <&k3_clks 292 11>;
-		};
-
-		wiz0_pll1_refclk: pll1-refclk {
-			clocks = <&k3_clks 292 0>, <&dummy_cmn_refclk1>;
-			#clock-cells = <0>;
-			assigned-clocks = <&wiz0_pll1_refclk>;
-			assigned-clock-parents = <&k3_clks 292 0>;
-		};
-
-		wiz0_refclk_dig: refclk-dig {
-			clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
-			#clock-cells = <0>;
-			assigned-clocks = <&wiz0_refclk_dig>;
-			assigned-clock-parents = <&k3_clks 292 11>;
-		};
-
-		wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
-			clocks = <&wiz0_refclk_dig>;
-			#clock-cells = <0>;
-		};
-
-		wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
-			clocks = <&wiz0_pll1_refclk>;
-			#clock-cells = <0>;
-		};
-
-		serdes0: serdes@5000000 {
-			compatible = "ti,sierra-phy-t0";
-			reg-names = "serdes";
-			reg = <0x5000000 0x10000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			resets = <&serdes_wiz0 0>;
-			reset-names = "sierra_reset";
-			clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
-			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
-		};
-	};
-
-	serdes_wiz1: wiz@5010000 {
-		compatible = "ti,j721e-wiz-16g";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&dummy_cmn_refclk>;
-		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
-		assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
-		assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
-		num-lanes = <2>;
-		#reset-cells = <1>;
-		ranges = <0x5010000 0x0 0x5010000 0x10000>;
-
-		wiz1_pll0_refclk: pll0-refclk {
-			clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
-			#clock-cells = <0>;
-			assigned-clocks = <&wiz1_pll0_refclk>;
-			assigned-clock-parents = <&k3_clks 293 13>;
-		};
-
-		wiz1_pll1_refclk: pll1-refclk {
-			clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
-			#clock-cells = <0>;
-			assigned-clocks = <&wiz1_pll1_refclk>;
-			assigned-clock-parents = <&k3_clks 293 0>;
-		};
-
-		wiz1_refclk_dig: refclk-dig {
-			clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
-			#clock-cells = <0>;
-			assigned-clocks = <&wiz1_refclk_dig>;
-			assigned-clock-parents = <&k3_clks 293 13>;
-		};
-
-		wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{
-			clocks = <&wiz1_refclk_dig>;
-			#clock-cells = <0>;
-		};
-
-		wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
-			clocks = <&wiz1_pll1_refclk>;
-			#clock-cells = <0>;
-		};
-
-		serdes1: serdes@5010000 {
-			compatible = "ti,sierra-phy-t0";
-			reg-names = "serdes";
-			reg = <0x5010000 0x10000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			resets = <&serdes_wiz1 0>;
-			reset-names = "sierra_reset";
-			clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>;
-			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
-		};
-	};
-
-	serdes_wiz2: wiz@5020000 {
-		compatible = "ti,j721e-wiz-16g";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&dummy_cmn_refclk>;
-		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
-		assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
-		assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
-		num-lanes = <2>;
-		#reset-cells = <1>;
-		ranges = <0x5020000 0x0 0x5020000 0x10000>;
-
-		wiz2_pll0_refclk: pll0-refclk {
-			clocks = <&k3_clks 294 11>, <&dummy_cmn_refclk>;
-			#clock-cells = <0>;
-			assigned-clocks = <&wiz2_pll0_refclk>;
-			assigned-clock-parents = <&k3_clks 294 11>;
-		};
-
-		wiz2_pll1_refclk: pll1-refclk {
-			clocks = <&k3_clks 294 0>, <&dummy_cmn_refclk1>;
-			#clock-cells = <0>;
-			assigned-clocks = <&wiz2_pll1_refclk>;
-			assigned-clock-parents = <&k3_clks 294 0>;
-		};
-
-		wiz2_refclk_dig: refclk-dig {
-			clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
-			#clock-cells = <0>;
-			assigned-clocks = <&wiz2_refclk_dig>;
-			assigned-clock-parents = <&k3_clks 294 11>;
-		};
-
-		wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div {
-			clocks = <&wiz2_refclk_dig>;
-			#clock-cells = <0>;
-		};
-
-		wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
-			clocks = <&wiz2_pll1_refclk>;
-			#clock-cells = <0>;
-		};
-
-		serdes2: serdes@5020000 {
-			compatible = "ti,sierra-phy-t0";
-			reg-names = "serdes";
-			reg = <0x5020000 0x10000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			resets = <&serdes_wiz2 0>;
-			reset-names = "sierra_reset";
-			clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>;
-			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
-		};
-	};
-
-	serdes_wiz3: wiz@5030000 {
-		compatible = "ti,j721e-wiz-16g";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&dummy_cmn_refclk>;
-		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
-		assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
-		assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
-		num-lanes = <2>;
-		#reset-cells = <1>;
-		ranges = <0x5030000 0x0 0x5030000 0x10000>;
-
-		wiz3_pll0_refclk: pll0-refclk {
-			clocks = <&k3_clks 295 9>, <&dummy_cmn_refclk>;
-			#clock-cells = <0>;
-			assigned-clocks = <&wiz3_pll0_refclk>;
-			assigned-clock-parents = <&k3_clks 295 9>;
-		};
-
-		wiz3_pll1_refclk: pll1-refclk {
-			clocks = <&k3_clks 295 0>, <&dummy_cmn_refclk1>;
-			#clock-cells = <0>;
-			assigned-clocks = <&wiz3_pll1_refclk>;
-			assigned-clock-parents = <&k3_clks 295 0>;
-		};
-
-		wiz3_refclk_dig: refclk-dig {
-			clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
-			#clock-cells = <0>;
-			assigned-clocks = <&wiz3_refclk_dig>;
-			assigned-clock-parents = <&k3_clks 295 9>;
-		};
-
-		wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div {
-			clocks = <&wiz3_refclk_dig>;
-			#clock-cells = <0>;
-		};
-
-		wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
-			clocks = <&wiz3_pll1_refclk>;
-			#clock-cells = <0>;
-		};
-
-		serdes3: serdes@5030000 {
-			compatible = "ti,sierra-phy-t0";
-			reg-names = "serdes";
-			reg = <0x5030000 0x10000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			resets = <&serdes_wiz3 0>;
-			reset-names = "sierra_reset";
-			clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>;
-			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
-		};
-	};
-
-	pcie0_rc: pcie@2900000 {
-		compatible = "ti,j721e-pcie-host";
-		reg = <0x00 0x02900000 0x00 0x1000>,
-		      <0x00 0x02907000 0x00 0x400>,
-		      <0x00 0x0d000000 0x00 0x00800000>,
-		      <0x00 0x10000000 0x00 0x00001000>;
-		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
-		ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
-		max-link-speed = <3>;
-		num-lanes = <2>;
-		power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 239 1>;
-		clock-names = "fck";
-		#address-cells = <3>;
-		#size-cells = <2>;
-		bus-range = <0x0 0xf>;
-		cdns,max-outbound-regions = <16>;
-		cdns,no-bar-match-nbits = <64>;
-		vendor-id = /bits/ 16 <0x104c>;
-		device-id = /bits/ 16 <0xb00d>;
-		msi-map = <0x0 &gic_its 0x0 0x10000>;
-		dma-coherent;
-		ranges = <0x01000000 0x0 0x10001000  0x00 0x10001000  0x0 0x0010000>,
-			 <0x02000000 0x0 0x10011000  0x00 0x10011000  0x0 0x7fef000>;
-		#interrupt-cells = <1>;
-		interrupt-map-mask = <0 0 0 7>;
-		interrupt-map = <0 0 0 1 &pcie0_intc 0>, /* INT A */
-				<0 0 0 2 &pcie0_intc 0>, /* INT B */
-				<0 0 0 3 &pcie0_intc 0>, /* INT C */
-				<0 0 0 4 &pcie0_intc 0>; /* INT D */
-
-		pcie0_intc: legacy-interrupt-controller {
-			interrupt-controller;
-			#interrupt-cells = <1>;
-			interrupt-parent = <&gic500>;
-			interrupts = <GIC_SPI 312 IRQ_TYPE_EDGE_RISING>;
-		};
-	};
-
-	pcie0_ep: pcie-ep@2900000 {
-		compatible = "ti,j721e-pcie-ep";
-		reg = <0x00 0x02900000 0x00 0x1000>,
-		      <0x00 0x02907000 0x00 0x400>,
-		      <0x00 0x0d000000 0x00 0x00800000>,
-		      <0x00 0x10000000 0x00 0x08000000>;
-		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
-		ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
-		max-link-speed = <3>;
-		num-lanes = <2>;
-		power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 239 1>;
-		clock-names = "fck";
-		cdns,max-outbound-regions = <16>;
-		max-functions = /bits/ 8 <6>;
-		max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
-		dma-coherent;
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-	};
-
-	pcie1_rc: pcie@2910000 {
-		compatible = "ti,j721e-pcie-host";
-		reg = <0x00 0x02910000 0x00 0x1000>,
-		      <0x00 0x02917000 0x00 0x400>,
-		      <0x00 0x0d800000 0x00 0x00800000>,
-		      <0x00 0x18000000 0x00 0x00001000>;
-		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
-		ti,syscon-pcie-ctrl = <&pcie1_ctrl>;
-		max-link-speed = <3>;
-		num-lanes = <2>;
-		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 240 1>;
-		clock-names = "fck";
-		#address-cells = <3>;
-		#size-cells = <2>;
-		bus-range = <0x0 0xf>;
-		cdns,max-outbound-regions = <16>;
-		cdns,no-bar-match-nbits = <64>;
-		vendor-id = /bits/ 16 <0x104c>;
-		device-id = /bits/ 16 <0xb00d>;
-		msi-map = <0x0 &gic_its 0x10000 0x10000>;
-		dma-coherent;
-		ranges = <0x01000000 0x0 0x18001000  0x00 0x18001000  0x0 0x0010000>,
-			 <0x02000000 0x0 0x18011000  0x00 0x18011000  0x0 0x7fef000>;
-		#interrupt-cells = <1>;
-		interrupt-map-mask = <0 0 0 7>;
-		interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */
-				<0 0 0 2 &pcie1_intc 0>, /* INT B */
-				<0 0 0 3 &pcie1_intc 0>, /* INT C */
-				<0 0 0 4 &pcie1_intc 0>; /* INT D */
-
-		pcie1_intc: legacy-interrupt-controller {
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			interrupt-parent = <&gic500>;
-			interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>;
-		};
-	};
-
-	pcie1_ep: pcie-ep@2910000 {
-		compatible = "ti,j721e-pcie-ep";
-		reg = <0x00 0x02910000 0x00 0x1000>,
-		      <0x00 0x02917000 0x00 0x400>,
-		      <0x00 0x0d800000 0x00 0x00800000>,
-		      <0x00 0x18000000 0x00 0x08000000>;
-		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
-		ti,syscon-pcie-ctrl = <&pcie1_ctrl>;
-		max-link-speed = <3>;
-		num-lanes = <2>;
-		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 240 1>;
-		clock-names = "fck";
-		cdns,max-outbound-regions = <16>;
-		max-functions = /bits/ 8 <6>;
-		max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
-		dma-coherent;
-	};
-
-	pcie2_rc: pcie@2920000 {
-		compatible = "ti,j721e-pcie-host";
-		reg = <0x00 0x02920000 0x00 0x1000>,
-		      <0x00 0x02927000 0x00 0x400>,
-		      <0x00 0x0e000000 0x00 0x00800000>,
-		      <0x44 0x00000000 0x00 0x00001000>;
-		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
-		ti,syscon-pcie-ctrl = <&pcie2_ctrl>;
-		max-link-speed = <3>;
-		num-lanes = <2>;
-		power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 241 1>;
-		clock-names = "fck";
-		#address-cells = <3>;
-		#size-cells = <2>;
-		bus-range = <0x0 0xf>;
-		cdns,max-outbound-regions = <16>;
-		cdns,no-bar-match-nbits = <64>;
-		vendor-id = /bits/ 16 <0x104c>;
-		device-id = /bits/ 16 <0xb00d>;
-		msi-map = <0x0 &gic_its 0x20000 0x10000>;
-		dma-coherent;
-		ranges = <0x01000000 0x00 0x00001000  0x44 0x00001000  0x0 0x0010000>,
-			 <0x02000000 0x00 0x00011000  0x44 0x00011000  0x0 0x7fef000>;
-		#interrupt-cells = <1>;
-		interrupt-map-mask = <0 0 0 7>;
-		interrupt-map = <0 0 0 1 &pcie2_intc 0>, /* INT A */
-				<0 0 0 2 &pcie2_intc 0>, /* INT B */
-				<0 0 0 3 &pcie2_intc 0>, /* INT C */
-				<0 0 0 4 &pcie2_intc 0>; /* INT D */
-
-		pcie2_intc: legacy-interrupt-controller {
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			interrupt-parent = <&gic500>;
-			interrupts = <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>;
-		};
-	};
-
-	pcie2_ep: pcie-ep@2920000 {
-		compatible = "ti,j721e-pcie-ep";
-		reg = <0x00 0x02920000 0x00 0x1000>,
-		      <0x00 0x02927000 0x00 0x400>,
-		      <0x00 0x0e000000 0x00 0x00800000>,
-		      <0x44 0x00000000 0x00 0x08000000>;
-		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
-		ti,syscon-pcie-ctrl = <&pcie2_ctrl>;
-		max-link-speed = <3>;
-		num-lanes = <2>;
-		power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 241 1>;
-		clock-names = "fck";
-		cdns,max-outbound-regions = <16>;
-		max-functions = /bits/ 8 <6>;
-		max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
-		dma-coherent;
-	};
-
-	pcie3_rc: pcie@2930000 {
-		compatible = "ti,j721e-pcie-host";
-		reg = <0x00 0x02930000 0x00 0x1000>,
-		      <0x00 0x02937000 0x00 0x400>,
-		      <0x00 0x0e800000 0x00 0x00800000>,
-		      <0x44 0x10000000 0x00 0x00001000>;
-		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
-		ti,syscon-pcie-ctrl = <&pcie3_ctrl>;
-		max-link-speed = <3>;
-		num-lanes = <2>;
-		power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 242 1>;
-		clock-names = "fck";
-		#address-cells = <3>;
-		#size-cells = <2>;
-		bus-range = <0x0 0xf>;
-		cdns,max-outbound-regions = <16>;
-		cdns,no-bar-match-nbits = <64>;
-		vendor-id = /bits/ 16 <0x104c>;
-		device-id = /bits/ 16 <0xb00d>;
-		msi-map = <0x0 &gic_its 0x30000 0x10000>;
-		dma-coherent;
-		ranges = <0x01000000 0x00 0x00001000  0x44 0x10001000  0x0 0x0010000>,
-			 <0x02000000 0x00 0x00011000  0x44 0x10011000  0x0 0x7fef000>;
-		#interrupt-cells = <1>;
-		interrupt-map-mask = <0 0 0 7>;
-		interrupt-map = <0 0 0 1 &pcie3_intc 0>, /* INT A */
-				<0 0 0 2 &pcie3_intc 0>, /* INT B */
-				<0 0 0 3 &pcie3_intc 0>, /* INT C */
-				<0 0 0 4 &pcie3_intc 0>; /* INT D */
-
-		pcie3_intc: legacy-interrupt-controller {
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			interrupt-parent = <&gic500>;
-			interrupts = <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>;
-		};
-	};
-
-	pcie3_ep: pcie-ep@2930000 {
-		compatible = "ti,j721e-pcie-ep";
-		reg = <0x00 0x02930000 0x00 0x1000>,
-		      <0x00 0x02937000 0x00 0x400>,
-		      <0x00 0x0e800000 0x00 0x00800000>,
-		      <0x44 0x10000000 0x00 0x08000000>;
-		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
-		ti,syscon-pcie-ctrl = <&pcie3_ctrl>;
-		max-link-speed = <3>;
-		num-lanes = <2>;
-		power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 242 1>;
-		clock-names = "fck";
-		cdns,max-outbound-regions = <16>;
-		max-functions = /bits/ 8 <6>;
-		max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
-		dma-coherent;
-		#address-cells = <2>;
-		#size-cells = <2>;
-	};
-
-	serdes_wiz4: wiz@5050000 {
-		compatible = "ti,j721e-wiz-10g";
-		#address-cells = <2>;
-		#size-cells = <2>;
-		power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&dummy_cmn_refclk>;
-		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
-		num-lanes = <4>;
-		#reset-cells = <1>;
-		ranges;
-
-		assigned-clocks = <&k3_clks 297 9>;
-		assigned-clock-parents = <&k3_clks 297 10>;
-		assigned-clock-rates = <19200000>;
-
-		wiz4_pll0_refclk: pll0-refclk {
-			clocks = <&k3_clks 297 9>, <&dummy_cmn_refclk>;
-			clock-output-names = "wiz4_pll0_refclk";
-			#clock-cells = <0>;
-			assigned-clocks = <&wiz4_pll0_refclk>;
-			assigned-clock-parents = <&k3_clks 297 9>;
-		};
-
-		wiz4_pll1_refclk: pll1-refclk {
-			clocks = <&k3_clks 297 9>, <&dummy_cmn_refclk>;
-			clock-output-names = "wiz4_pll1_refclk";
-			#clock-cells = <0>;
-			assigned-clocks = <&wiz4_pll1_refclk>;
-			assigned-clock-parents = <&k3_clks 297 9>;
-		};
-
-		wiz4_refclk_dig: refclk-dig {
-			clocks = <&k3_clks 297 9>, <&dummy_cmn_refclk>;
-			clock-output-names = "wiz4_refclk_dig";
-			#clock-cells = <0>;
-			assigned-clocks = <&wiz4_refclk_dig>;
-			assigned-clock-parents = <&k3_clks 297 9>;
-		};
-
-		wiz4_cmn_refclk_dig_div: cmn-refclk-dig-div {
-			clocks = <&wiz4_refclk_dig>;
-			#clock-cells = <0>;
-		};
-
-		wiz4_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
-			clocks = <&wiz4_pll1_refclk>;
-			#clock-cells = <0>;
-		};
-
-		serdes4: serdes@5050000 {
-			/* XXX we also map EDP0 registers here as the PHY driver needs those... */
-			compatible = "ti,j721e-serdes-10g";
-			reg = <0x00 0x05050000 0x0 0x00010000>, /* SERDES_10G0 */
-			      <0x00 0x0A030A00 0x0 0x00000040>; /* DSS_EDP0_V2A_CORE_VP_REGS_APB + 30A00 */
-
-			resets = <&serdes_wiz4 0>;
-			reset-names = "torrent_reset";
-			clocks = <&wiz4_pll0_refclk>;
-			clock-names = "refclk";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			torrent_phy_dp: link@0{
-				reg = <0>;
-				resets = <&serdes_wiz4 1>;
-				cdns,phy-type = <PHY_TYPE_DP>;
-				cdns,num-lanes = <4>;
-				cdns,max-bit-rate = <5400>;
-				#phy-cells = <0>;
-			};
-		};
-	};
-
-	mhdp: dp-bridge@000A000000 {
-		compatible = "ti,j721e-mhdp8546", "cdns,mhdp8546";
-		reg = <0x00 0x0A000000 0x0 0x30A00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB - upto PHY mapped area */
-		      <0x00 0x04F40000 0x0 0x20>;    /* DSS_EDP0_INTG_CFG_VP */
-
-		status = "disabled";
-
-		clocks = <&k3_clks 151 36>;
-
-		phys = <&torrent_phy_dp>;
-		phy-names = "dpphy";
-
-		interrupt-parent = <&gic500>;
-		interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
-
-		power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
-
-		/* TODO: No audio config yet */
-
-		dp0_ports: ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-	};
+	// serdes_wiz0: wiz@5000000 {
+	// 	compatible = "ti,j721e-wiz-16g";
+	// 	#address-cells = <1>;
+	// 	#size-cells = <1>;
+	// 	power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
+	// 	clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+	// 	assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
+	// 	assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
+	// 	num-lanes = <2>;
+	// 	#reset-cells = <1>;
+	// 	ranges = <0x5000000 0x0 0x5000000 0x10000>;
+
+	// 	wiz0_pll0_refclk: pll0-refclk {
+	// 		clocks = <&k3_clks 292 11>, <&dummy_cmn_refclk>;
+	// 		#clock-cells = <0>;
+	// 		assigned-clocks = <&wiz0_pll0_refclk>;
+	// 		assigned-clock-parents = <&k3_clks 292 11>;
+	// 	};
+
+	// 	wiz0_pll1_refclk: pll1-refclk {
+	// 		clocks = <&k3_clks 292 0>, <&dummy_cmn_refclk1>;
+	// 		#clock-cells = <0>;
+	// 		assigned-clocks = <&wiz0_pll1_refclk>;
+	// 		assigned-clock-parents = <&k3_clks 292 0>;
+	// 	};
+
+	// 	wiz0_refclk_dig: refclk-dig {
+	// 		clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
+	// 		#clock-cells = <0>;
+	// 		assigned-clocks = <&wiz0_refclk_dig>;
+	// 		assigned-clock-parents = <&k3_clks 292 11>;
+	// 	};
+
+	// 	wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
+	// 		clocks = <&wiz0_refclk_dig>;
+	// 		#clock-cells = <0>;
+	// 	};
+
+	// 	wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
+	// 		clocks = <&wiz0_pll1_refclk>;
+	// 		#clock-cells = <0>;
+	// 	};
+
+	// 	serdes0: serdes@5000000 {
+	// 		compatible = "ti,sierra-phy-t0";
+	// 		reg-names = "serdes";
+	// 		reg = <0x5000000 0x10000>;
+	// 		#address-cells = <1>;
+	// 		#size-cells = <0>;
+	// 		resets = <&serdes_wiz0 0>;
+	// 		reset-names = "sierra_reset";
+	// 		clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
+	// 		clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+	// 	};
+	// };
+
+	// serdes_wiz1: wiz@5010000 {
+	// 	compatible = "ti,j721e-wiz-16g";
+	// 	#address-cells = <1>;
+	// 	#size-cells = <1>;
+	// 	power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&dummy_cmn_refclk>;
+	// 	clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+	// 	assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
+	// 	assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
+	// 	num-lanes = <2>;
+	// 	#reset-cells = <1>;
+	// 	ranges = <0x5010000 0x0 0x5010000 0x10000>;
+
+	// 	wiz1_pll0_refclk: pll0-refclk {
+	// 		clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
+	// 		#clock-cells = <0>;
+	// 		assigned-clocks = <&wiz1_pll0_refclk>;
+	// 		assigned-clock-parents = <&k3_clks 293 13>;
+	// 	};
+
+	// 	wiz1_pll1_refclk: pll1-refclk {
+	// 		clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
+	// 		#clock-cells = <0>;
+	// 		assigned-clocks = <&wiz1_pll1_refclk>;
+	// 		assigned-clock-parents = <&k3_clks 293 0>;
+	// 	};
+
+	// 	wiz1_refclk_dig: refclk-dig {
+	// 		clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
+	// 		#clock-cells = <0>;
+	// 		assigned-clocks = <&wiz1_refclk_dig>;
+	// 		assigned-clock-parents = <&k3_clks 293 13>;
+	// 	};
+
+	// 	wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{
+	// 		clocks = <&wiz1_refclk_dig>;
+	// 		#clock-cells = <0>;
+	// 	};
+
+	// 	wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
+	// 		clocks = <&wiz1_pll1_refclk>;
+	// 		#clock-cells = <0>;
+	// 	};
+
+	// 	serdes1: serdes@5010000 {
+	// 		compatible = "ti,sierra-phy-t0";
+	// 		reg-names = "serdes";
+	// 		reg = <0x5010000 0x10000>;
+	// 		#address-cells = <1>;
+	// 		#size-cells = <0>;
+	// 		resets = <&serdes_wiz1 0>;
+	// 		reset-names = "sierra_reset";
+	// 		clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>;
+	// 		clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+	// 	};
+	// };
+
+	// serdes_wiz2: wiz@5020000 {
+	// 	compatible = "ti,j721e-wiz-16g";
+	// 	#address-cells = <1>;
+	// 	#size-cells = <1>;
+	// 	power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&dummy_cmn_refclk>;
+	// 	clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+	// 	assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
+	// 	assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
+	// 	num-lanes = <2>;
+	// 	#reset-cells = <1>;
+	// 	ranges = <0x5020000 0x0 0x5020000 0x10000>;
+
+	// 	wiz2_pll0_refclk: pll0-refclk {
+	// 		clocks = <&k3_clks 294 11>, <&dummy_cmn_refclk>;
+	// 		#clock-cells = <0>;
+	// 		assigned-clocks = <&wiz2_pll0_refclk>;
+	// 		assigned-clock-parents = <&k3_clks 294 11>;
+	// 	};
+
+	// 	wiz2_pll1_refclk: pll1-refclk {
+	// 		clocks = <&k3_clks 294 0>, <&dummy_cmn_refclk1>;
+	// 		#clock-cells = <0>;
+	// 		assigned-clocks = <&wiz2_pll1_refclk>;
+	// 		assigned-clock-parents = <&k3_clks 294 0>;
+	// 	};
+
+	// 	wiz2_refclk_dig: refclk-dig {
+	// 		clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
+	// 		#clock-cells = <0>;
+	// 		assigned-clocks = <&wiz2_refclk_dig>;
+	// 		assigned-clock-parents = <&k3_clks 294 11>;
+	// 	};
+
+	// 	wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div {
+	// 		clocks = <&wiz2_refclk_dig>;
+	// 		#clock-cells = <0>;
+	// 	};
+
+	// 	wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
+	// 		clocks = <&wiz2_pll1_refclk>;
+	// 		#clock-cells = <0>;
+	// 	};
+
+	// 	serdes2: serdes@5020000 {
+	// 		compatible = "ti,sierra-phy-t0";
+	// 		reg-names = "serdes";
+	// 		reg = <0x5020000 0x10000>;
+	// 		#address-cells = <1>;
+	// 		#size-cells = <0>;
+	// 		resets = <&serdes_wiz2 0>;
+	// 		reset-names = "sierra_reset";
+	// 		clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>;
+	// 		clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+	// 	};
+	// };
+
+	// serdes_wiz3: wiz@5030000 {
+	// 	compatible = "ti,j721e-wiz-16g";
+	// 	#address-cells = <1>;
+	// 	#size-cells = <1>;
+	// 	power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&dummy_cmn_refclk>;
+	// 	clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+	// 	assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
+	// 	assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
+	// 	num-lanes = <2>;
+	// 	#reset-cells = <1>;
+	// 	ranges = <0x5030000 0x0 0x5030000 0x10000>;
+
+	// 	wiz3_pll0_refclk: pll0-refclk {
+	// 		clocks = <&k3_clks 295 9>, <&dummy_cmn_refclk>;
+	// 		#clock-cells = <0>;
+	// 		assigned-clocks = <&wiz3_pll0_refclk>;
+	// 		assigned-clock-parents = <&k3_clks 295 9>;
+	// 	};
+
+	// 	wiz3_pll1_refclk: pll1-refclk {
+	// 		clocks = <&k3_clks 295 0>, <&dummy_cmn_refclk1>;
+	// 		#clock-cells = <0>;
+	// 		assigned-clocks = <&wiz3_pll1_refclk>;
+	// 		assigned-clock-parents = <&k3_clks 295 0>;
+	// 	};
+
+	// 	wiz3_refclk_dig: refclk-dig {
+	// 		clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
+	// 		#clock-cells = <0>;
+	// 		assigned-clocks = <&wiz3_refclk_dig>;
+	// 		assigned-clock-parents = <&k3_clks 295 9>;
+	// 	};
+
+	// 	wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div {
+	// 		clocks = <&wiz3_refclk_dig>;
+	// 		#clock-cells = <0>;
+	// 	};
+
+	// 	wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
+	// 		clocks = <&wiz3_pll1_refclk>;
+	// 		#clock-cells = <0>;
+	// 	};
+
+	// 	serdes3: serdes@5030000 {
+	// 		compatible = "ti,sierra-phy-t0";
+	// 		reg-names = "serdes";
+	// 		reg = <0x5030000 0x10000>;
+	// 		#address-cells = <1>;
+	// 		#size-cells = <0>;
+	// 		resets = <&serdes_wiz3 0>;
+	// 		reset-names = "sierra_reset";
+	// 		clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>;
+	// 		clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+	// 	};
+	// };
+
+	// pcie0_rc: pcie@2900000 {
+	// 	compatible = "ti,j721e-pcie-host";
+	// 	reg = <0x00 0x02900000 0x00 0x1000>,
+	// 	      <0x00 0x02907000 0x00 0x400>,
+	// 	      <0x00 0x0d000000 0x00 0x00800000>,
+	// 	      <0x00 0x10000000 0x00 0x00001000>;
+	// 	reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+	// 	ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
+	// 	max-link-speed = <3>;
+	// 	num-lanes = <2>;
+	// 	power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 239 1>;
+	// 	clock-names = "fck";
+	// 	#address-cells = <3>;
+	// 	#size-cells = <2>;
+	// 	bus-range = <0x0 0xf>;
+	// 	cdns,max-outbound-regions = <16>;
+	// 	cdns,no-bar-match-nbits = <64>;
+	// 	vendor-id = /bits/ 16 <0x104c>;
+	// 	device-id = /bits/ 16 <0xb00d>;
+	// 	msi-map = <0x0 &gic_its 0x0 0x10000>;
+	// 	dma-coherent;
+	// 	ranges = <0x01000000 0x0 0x10001000  0x00 0x10001000  0x0 0x0010000>,
+	// 		 <0x02000000 0x0 0x10011000  0x00 0x10011000  0x0 0x7fef000>;
+	// 	#interrupt-cells = <1>;
+	// 	interrupt-map-mask = <0 0 0 7>;
+	// 	interrupt-map = <0 0 0 1 &pcie0_intc 0>, /* INT A */
+	// 			<0 0 0 2 &pcie0_intc 0>, /* INT B */
+	// 			<0 0 0 3 &pcie0_intc 0>, /* INT C */
+	// 			<0 0 0 4 &pcie0_intc 0>; /* INT D */
+
+	// 	pcie0_intc: legacy-interrupt-controller {
+	// 		interrupt-controller;
+	// 		#interrupt-cells = <1>;
+	// 		interrupt-parent = <&gic500>;
+	// 		interrupts = <GIC_SPI 312 IRQ_TYPE_EDGE_RISING>;
+	// 	};
+	// };
+
+	// pcie0_ep: pcie-ep@2900000 {
+	// 	compatible = "ti,j721e-pcie-ep";
+	// 	reg = <0x00 0x02900000 0x00 0x1000>,
+	// 	      <0x00 0x02907000 0x00 0x400>,
+	// 	      <0x00 0x0d000000 0x00 0x00800000>,
+	// 	      <0x00 0x10000000 0x00 0x08000000>;
+	// 	reg-names = "intd_cfg", "user_cfg", "reg", "mem";
+	// 	ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
+	// 	max-link-speed = <3>;
+	// 	num-lanes = <2>;
+	// 	power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 239 1>;
+	// 	clock-names = "fck";
+	// 	cdns,max-outbound-regions = <16>;
+	// 	max-functions = /bits/ 8 <6>;
+	// 	max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
+	// 	dma-coherent;
+	// 	#address-cells = <2>;
+	// 	#size-cells = <2>;
+	// 	ranges;
+	// };
+
+	// pcie1_rc: pcie@2910000 {
+	// 	compatible = "ti,j721e-pcie-host";
+	// 	reg = <0x00 0x02910000 0x00 0x1000>,
+	// 	      <0x00 0x02917000 0x00 0x400>,
+	// 	      <0x00 0x0d800000 0x00 0x00800000>,
+	// 	      <0x00 0x18000000 0x00 0x00001000>;
+	// 	reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+	// 	ti,syscon-pcie-ctrl = <&pcie1_ctrl>;
+	// 	max-link-speed = <3>;
+	// 	num-lanes = <2>;
+	// 	power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 240 1>;
+	// 	clock-names = "fck";
+	// 	#address-cells = <3>;
+	// 	#size-cells = <2>;
+	// 	bus-range = <0x0 0xf>;
+	// 	cdns,max-outbound-regions = <16>;
+	// 	cdns,no-bar-match-nbits = <64>;
+	// 	vendor-id = /bits/ 16 <0x104c>;
+	// 	device-id = /bits/ 16 <0xb00d>;
+	// 	msi-map = <0x0 &gic_its 0x10000 0x10000>;
+	// 	dma-coherent;
+	// 	ranges = <0x01000000 0x0 0x18001000  0x00 0x18001000  0x0 0x0010000>,
+	// 		 <0x02000000 0x0 0x18011000  0x00 0x18011000  0x0 0x7fef000>;
+	// 	#interrupt-cells = <1>;
+	// 	interrupt-map-mask = <0 0 0 7>;
+	// 	interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */
+	// 			<0 0 0 2 &pcie1_intc 0>, /* INT B */
+	// 			<0 0 0 3 &pcie1_intc 0>, /* INT C */
+	// 			<0 0 0 4 &pcie1_intc 0>; /* INT D */
+
+	// 	pcie1_intc: legacy-interrupt-controller {
+	// 		interrupt-controller;
+	// 		#interrupt-cells = <2>;
+	// 		interrupt-parent = <&gic500>;
+	// 		interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>;
+	// 	};
+	// };
+
+	// pcie1_ep: pcie-ep@2910000 {
+	// 	compatible = "ti,j721e-pcie-ep";
+	// 	reg = <0x00 0x02910000 0x00 0x1000>,
+	// 	      <0x00 0x02917000 0x00 0x400>,
+	// 	      <0x00 0x0d800000 0x00 0x00800000>,
+	// 	      <0x00 0x18000000 0x00 0x08000000>;
+	// 	reg-names = "intd_cfg", "user_cfg", "reg", "mem";
+	// 	ti,syscon-pcie-ctrl = <&pcie1_ctrl>;
+	// 	max-link-speed = <3>;
+	// 	num-lanes = <2>;
+	// 	power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 240 1>;
+	// 	clock-names = "fck";
+	// 	cdns,max-outbound-regions = <16>;
+	// 	max-functions = /bits/ 8 <6>;
+	// 	max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
+	// 	dma-coherent;
+	// };
+
+	// pcie2_rc: pcie@2920000 {
+	// 	compatible = "ti,j721e-pcie-host";
+	// 	reg = <0x00 0x02920000 0x00 0x1000>,
+	// 	      <0x00 0x02927000 0x00 0x400>,
+	// 	      <0x00 0x0e000000 0x00 0x00800000>,
+	// 	      <0x44 0x00000000 0x00 0x00001000>;
+	// 	reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+	// 	ti,syscon-pcie-ctrl = <&pcie2_ctrl>;
+	// 	max-link-speed = <3>;
+	// 	num-lanes = <2>;
+	// 	power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 241 1>;
+	// 	clock-names = "fck";
+	// 	#address-cells = <3>;
+	// 	#size-cells = <2>;
+	// 	bus-range = <0x0 0xf>;
+	// 	cdns,max-outbound-regions = <16>;
+	// 	cdns,no-bar-match-nbits = <64>;
+	// 	vendor-id = /bits/ 16 <0x104c>;
+	// 	device-id = /bits/ 16 <0xb00d>;
+	// 	msi-map = <0x0 &gic_its 0x20000 0x10000>;
+	// 	dma-coherent;
+	// 	ranges = <0x01000000 0x00 0x00001000  0x44 0x00001000  0x0 0x0010000>,
+	// 		 <0x02000000 0x00 0x00011000  0x44 0x00011000  0x0 0x7fef000>;
+	// 	#interrupt-cells = <1>;
+	// 	interrupt-map-mask = <0 0 0 7>;
+	// 	interrupt-map = <0 0 0 1 &pcie2_intc 0>, /* INT A */
+	// 			<0 0 0 2 &pcie2_intc 0>, /* INT B */
+	// 			<0 0 0 3 &pcie2_intc 0>, /* INT C */
+	// 			<0 0 0 4 &pcie2_intc 0>; /* INT D */
+
+	// 	pcie2_intc: legacy-interrupt-controller {
+	// 		interrupt-controller;
+	// 		#interrupt-cells = <2>;
+	// 		interrupt-parent = <&gic500>;
+	// 		interrupts = <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>;
+	// 	};
+	// };
+
+	// pcie2_ep: pcie-ep@2920000 {
+	// 	compatible = "ti,j721e-pcie-ep";
+	// 	reg = <0x00 0x02920000 0x00 0x1000>,
+	// 	      <0x00 0x02927000 0x00 0x400>,
+	// 	      <0x00 0x0e000000 0x00 0x00800000>,
+	// 	      <0x44 0x00000000 0x00 0x08000000>;
+	// 	reg-names = "intd_cfg", "user_cfg", "reg", "mem";
+	// 	ti,syscon-pcie-ctrl = <&pcie2_ctrl>;
+	// 	max-link-speed = <3>;
+	// 	num-lanes = <2>;
+	// 	power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 241 1>;
+	// 	clock-names = "fck";
+	// 	cdns,max-outbound-regions = <16>;
+	// 	max-functions = /bits/ 8 <6>;
+	// 	max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
+	// 	dma-coherent;
+	// };
+
+	// pcie3_rc: pcie@2930000 {
+	// 	compatible = "ti,j721e-pcie-host";
+	// 	reg = <0x00 0x02930000 0x00 0x1000>,
+	// 	      <0x00 0x02937000 0x00 0x400>,
+	// 	      <0x00 0x0e800000 0x00 0x00800000>,
+	// 	      <0x44 0x10000000 0x00 0x00001000>;
+	// 	reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+	// 	ti,syscon-pcie-ctrl = <&pcie3_ctrl>;
+	// 	max-link-speed = <3>;
+	// 	num-lanes = <2>;
+	// 	power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 242 1>;
+	// 	clock-names = "fck";
+	// 	#address-cells = <3>;
+	// 	#size-cells = <2>;
+	// 	bus-range = <0x0 0xf>;
+	// 	cdns,max-outbound-regions = <16>;
+	// 	cdns,no-bar-match-nbits = <64>;
+	// 	vendor-id = /bits/ 16 <0x104c>;
+	// 	device-id = /bits/ 16 <0xb00d>;
+	// 	msi-map = <0x0 &gic_its 0x30000 0x10000>;
+	// 	dma-coherent;
+	// 	ranges = <0x01000000 0x00 0x00001000  0x44 0x10001000  0x0 0x0010000>,
+	// 		 <0x02000000 0x00 0x00011000  0x44 0x10011000  0x0 0x7fef000>;
+	// 	#interrupt-cells = <1>;
+	// 	interrupt-map-mask = <0 0 0 7>;
+	// 	interrupt-map = <0 0 0 1 &pcie3_intc 0>, /* INT A */
+	// 			<0 0 0 2 &pcie3_intc 0>, /* INT B */
+	// 			<0 0 0 3 &pcie3_intc 0>, /* INT C */
+	// 			<0 0 0 4 &pcie3_intc 0>; /* INT D */
+
+	// 	pcie3_intc: legacy-interrupt-controller {
+	// 		interrupt-controller;
+	// 		#interrupt-cells = <2>;
+	// 		interrupt-parent = <&gic500>;
+	// 		interrupts = <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>;
+	// 	};
+	// };
+
+	// pcie3_ep: pcie-ep@2930000 {
+	// 	compatible = "ti,j721e-pcie-ep";
+	// 	reg = <0x00 0x02930000 0x00 0x1000>,
+	// 	      <0x00 0x02937000 0x00 0x400>,
+	// 	      <0x00 0x0e800000 0x00 0x00800000>,
+	// 	      <0x44 0x10000000 0x00 0x08000000>;
+	// 	reg-names = "intd_cfg", "user_cfg", "reg", "mem";
+	// 	ti,syscon-pcie-ctrl = <&pcie3_ctrl>;
+	// 	max-link-speed = <3>;
+	// 	num-lanes = <2>;
+	// 	power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 242 1>;
+	// 	clock-names = "fck";
+	// 	cdns,max-outbound-regions = <16>;
+	// 	max-functions = /bits/ 8 <6>;
+	// 	max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
+	// 	dma-coherent;
+	// 	#address-cells = <2>;
+	// 	#size-cells = <2>;
+	// };
+
+	// serdes_wiz4: wiz@5050000 {
+	// 	compatible = "ti,j721e-wiz-10g";
+	// 	#address-cells = <2>;
+	// 	#size-cells = <2>;
+	// 	power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&dummy_cmn_refclk>;
+	// 	clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+	// 	num-lanes = <4>;
+	// 	#reset-cells = <1>;
+	// 	ranges;
+
+	// 	assigned-clocks = <&k3_clks 297 9>;
+	// 	assigned-clock-parents = <&k3_clks 297 10>;
+	// 	assigned-clock-rates = <19200000>;
+
+	// 	wiz4_pll0_refclk: pll0-refclk {
+	// 		clocks = <&k3_clks 297 9>, <&dummy_cmn_refclk>;
+	// 		clock-output-names = "wiz4_pll0_refclk";
+	// 		#clock-cells = <0>;
+	// 		assigned-clocks = <&wiz4_pll0_refclk>;
+	// 		assigned-clock-parents = <&k3_clks 297 9>;
+	// 	};
+
+	// 	wiz4_pll1_refclk: pll1-refclk {
+	// 		clocks = <&k3_clks 297 9>, <&dummy_cmn_refclk>;
+	// 		clock-output-names = "wiz4_pll1_refclk";
+	// 		#clock-cells = <0>;
+	// 		assigned-clocks = <&wiz4_pll1_refclk>;
+	// 		assigned-clock-parents = <&k3_clks 297 9>;
+	// 	};
+
+	// 	wiz4_refclk_dig: refclk-dig {
+	// 		clocks = <&k3_clks 297 9>, <&dummy_cmn_refclk>;
+	// 		clock-output-names = "wiz4_refclk_dig";
+	// 		#clock-cells = <0>;
+	// 		assigned-clocks = <&wiz4_refclk_dig>;
+	// 		assigned-clock-parents = <&k3_clks 297 9>;
+	// 	};
+
+	// 	wiz4_cmn_refclk_dig_div: cmn-refclk-dig-div {
+	// 		clocks = <&wiz4_refclk_dig>;
+	// 		#clock-cells = <0>;
+	// 	};
+
+	// 	wiz4_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
+	// 		clocks = <&wiz4_pll1_refclk>;
+	// 		#clock-cells = <0>;
+	// 	};
+
+	// 	serdes4: serdes@5050000 {
+	// 		/* XXX we also map EDP0 registers here as the PHY driver needs those... */
+	// 		compatible = "ti,j721e-serdes-10g";
+	// 		reg = <0x00 0x05050000 0x0 0x00010000>, /* SERDES_10G0 */
+	// 		      <0x00 0x0A030A00 0x0 0x00000040>; /* DSS_EDP0_V2A_CORE_VP_REGS_APB + 30A00 */
+
+	// 		resets = <&serdes_wiz4 0>;
+	// 		reset-names = "torrent_reset";
+	// 		clocks = <&wiz4_pll0_refclk>;
+	// 		clock-names = "refclk";
+	// 		#address-cells = <1>;
+	// 		#size-cells = <0>;
+	// 		torrent_phy_dp: link@0{
+	// 			reg = <0>;
+	// 			resets = <&serdes_wiz4 1>;
+	// 			cdns,phy-type = <PHY_TYPE_DP>;
+	// 			cdns,num-lanes = <4>;
+	// 			cdns,max-bit-rate = <5400>;
+	// 			#phy-cells = <0>;
+	// 		};
+	// 	};
+	// };
+
+	// mhdp: dp-bridge@000A000000 {
+	// 	compatible = "ti,j721e-mhdp8546", "cdns,mhdp8546";
+	// 	reg = <0x00 0x0A000000 0x0 0x30A00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB - upto PHY mapped area */
+	// 	      <0x00 0x04F40000 0x0 0x20>;    /* DSS_EDP0_INTG_CFG_VP */
+
+	// 	status = "disabled";
+
+	// 	clocks = <&k3_clks 151 36>;
+
+	// 	phys = <&torrent_phy_dp>;
+	// 	phy-names = "dpphy";
+
+	// 	interrupt-parent = <&gic500>;
+	// 	interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
+
+	// 	power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
+
+	// 	/* TODO: No audio config yet */
+
+	// 	dp0_ports: ports {
+	// 		#address-cells = <1>;
+	// 		#size-cells = <0>;
+	// 	};
+	// };
 
 	main_uart0: serial@2800000 {
 		compatible = "ti,j721e-uart", "ti,am654-uart";
@@ -996,349 +996,349 @@
 		clock-names = "fclk";
 	};
 
-	main_uart1: serial@2810000 {
-		compatible = "ti,j721e-uart", "ti,am654-uart";
-		reg = <0x00 0x02810000 0x00 0x100>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <48000000>;
-		current-speed = <115200>;
-		power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 278 0>;
-		clock-names = "fclk";
-	};
-
-	main_uart2: serial@2820000 {
-		compatible = "ti,j721e-uart", "ti,am654-uart";
-		reg = <0x00 0x02820000 0x00 0x100>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <48000000>;
-		current-speed = <115200>;
-		power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 279 0>;
-		clock-names = "fclk";
-	};
-
-	main_uart3: serial@2830000 {
-		compatible = "ti,j721e-uart", "ti,am654-uart";
-		reg = <0x00 0x02830000 0x00 0x100>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <48000000>;
-		current-speed = <115200>;
-		power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 280 0>;
-		clock-names = "fclk";
-	};
-
-	main_uart4: serial@2840000 {
-		compatible = "ti,j721e-uart", "ti,am654-uart";
-		reg = <0x00 0x02840000 0x00 0x100>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <48000000>;
-		current-speed = <115200>;
-		power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 281 0>;
-		clock-names = "fclk";
-	};
-
-	main_uart5: serial@2850000 {
-		compatible = "ti,j721e-uart", "ti,am654-uart";
-		reg = <0x00 0x02850000 0x00 0x100>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <48000000>;
-		current-speed = <115200>;
-		power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 282 0>;
-		clock-names = "fclk";
-	};
-
-	main_uart6: serial@2860000 {
-		compatible = "ti,j721e-uart", "ti,am654-uart";
-		reg = <0x00 0x02860000 0x00 0x100>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <48000000>;
-		current-speed = <115200>;
-		power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 283 0>;
-		clock-names = "fclk";
-	};
-
-	main_uart7: serial@2870000 {
-		compatible = "ti,j721e-uart", "ti,am654-uart";
-		reg = <0x00 0x02870000 0x00 0x100>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <48000000>;
-		current-speed = <115200>;
-		power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 284 0>;
-		clock-names = "fclk";
-	};
-
-	main_uart8: serial@2880000 {
-		compatible = "ti,j721e-uart", "ti,am654-uart";
-		reg = <0x00 0x02880000 0x00 0x100>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <48000000>;
-		current-speed = <115200>;
-		power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 285 0>;
-		clock-names = "fclk";
-	};
-
-	main_uart9: serial@2890000 {
-		compatible = "ti,j721e-uart", "ti,am654-uart";
-		reg = <0x00 0x02890000 0x00 0x100>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <48000000>;
-		current-speed = <115200>;
-		power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 286 0>;
-		clock-names = "fclk";
-	};
-
-	main_gpio0: gpio@600000 {
-		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
-		reg = <0x0 0x00600000 0x0 0x100>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		interrupt-parent = <&main_gpio_intr>;
-		interrupts = <256>, <257>, <258>, <259>,
-			     <260>, <261>, <262>, <263>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		ti,ngpio = <128>;
-		ti,davinci-gpio-unbanked = <0>;
-		power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 105 0>;
-		clock-names = "gpio";
-	};
-
-	main_gpio1: gpio@601000 {
-		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
-		reg = <0x0 0x00601000 0x0 0x100>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		interrupt-parent = <&main_gpio_intr>;
-		interrupts = <288>, <289>, <290>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		ti,ngpio = <36>;
-		ti,davinci-gpio-unbanked = <0>;
-		power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 106 0>;
-		clock-names = "gpio";
-	};
-
-	main_gpio2: gpio@610000 {
-		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
-		reg = <0x0 0x00610000 0x0 0x100>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		interrupt-parent = <&main_gpio_intr>;
-		interrupts = <264>, <265>, <266>, <267>,
-			     <268>, <269>, <270>, <271>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		ti,ngpio = <128>;
-		ti,davinci-gpio-unbanked = <0>;
-		power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 107 0>;
-		clock-names = "gpio";
-	};
-
-	main_gpio3: gpio@611000 {
-		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
-		reg = <0x0 0x00611000 0x0 0x100>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		interrupt-parent = <&main_gpio_intr>;
-		interrupts = <292>, <293>, <294>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		ti,ngpio = <36>;
-		ti,davinci-gpio-unbanked = <0>;
-		power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 108 0>;
-		clock-names = "gpio";
-	};
-
-	main_gpio4: gpio@620000 {
-		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
-		reg = <0x0 0x00620000 0x0 0x100>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		interrupt-parent = <&main_gpio_intr>;
-		interrupts = <272>, <273>, <274>, <275>,
-			     <276>, <277>, <278>, <279>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		ti,ngpio = <128>;
-		ti,davinci-gpio-unbanked = <0>;
-		power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 109 0>;
-		clock-names = "gpio";
-	};
-
-	main_gpio5: gpio@621000 {
-		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
-		reg = <0x0 0x00621000 0x0 0x100>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		interrupt-parent = <&main_gpio_intr>;
-		interrupts = <296>, <297>, <298>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		ti,ngpio = <36>;
-		ti,davinci-gpio-unbanked = <0>;
-		power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 110 0>;
-		clock-names = "gpio";
-	};
-
-	main_gpio6: gpio@630000 {
-		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
-		reg = <0x0 0x00630000 0x0 0x100>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		interrupt-parent = <&main_gpio_intr>;
-		interrupts = <280>, <281>, <282>, <283>,
-			     <284>, <285>, <286>, <287>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		ti,ngpio = <128>;
-		ti,davinci-gpio-unbanked = <0>;
-		power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 111 0>;
-		clock-names = "gpio";
-	};
-
-	main_gpio7: gpio@631000 {
-		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
-		reg = <0x0 0x00631000 0x0 0x100>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		interrupt-parent = <&main_gpio_intr>;
-		interrupts = <300>, <301>, <302>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		ti,ngpio = <36>;
-		ti,davinci-gpio-unbanked = <0>;
-		power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 112 0>;
-		clock-names = "gpio";
-	};
-
-	main_rti0: watchdog@2200000 {
-		compatible = "ti,rti-wdt";
-		reg = <0x0 0x2200000 0x0 0x100>;
-		clocks = <&k3_clks 252 1>;
-		power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
-		assigned-clocks = <&k3_clks 252 1>;
-		assigned-clock-parents = <&k3_clks 252 5>;
-	};
-
-	main_rti1: watchdog@2210000 {
-		compatible = "ti,rti-wdt";
-		reg = <0x0 0x2210000 0x0 0x100>;
-		clocks = <&k3_clks 253 1>;
-		power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
-		assigned-clocks = <&k3_clks 253 1>;
-		assigned-clock-parents = <&k3_clks 253 5>;
-	};
-
-	main_i2c0: i2c@2000000 {
-		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
-		reg = <0x0 0x2000000 0x0 0x100>;
-		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clock-names = "fck";
-		clocks = <&k3_clks 187 0>;
-		power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
-	};
-
-	main_i2c1: i2c@2010000 {
-		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
-		reg = <0x0 0x2010000 0x0 0x100>;
-		interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clock-names = "fck";
-		clocks = <&k3_clks 188 0>;
-		power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
-	};
-
-	main_i2c2: i2c@2020000 {
-		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
-		reg = <0x0 0x2020000 0x0 0x100>;
-		interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clock-names = "fck";
-		clocks = <&k3_clks 189 0>;
-		power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
-	};
-
-	main_i2c3: i2c@2030000 {
-		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
-		reg = <0x0 0x2030000 0x0 0x100>;
-		interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clock-names = "fck";
-		clocks = <&k3_clks 190 0>;
-		power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
-	};
-
-	main_i2c4: i2c@2040000 {
-		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
-		reg = <0x0 0x2040000 0x0 0x100>;
-		interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clock-names = "fck";
-		clocks = <&k3_clks 191 0>;
-		power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
-	};
-
-	main_i2c5: i2c@2050000 {
-		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
-		reg = <0x0 0x2050000 0x0 0x100>;
-		interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clock-names = "fck";
-		clocks = <&k3_clks 192 0>;
-		power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
-	};
-
-	main_i2c6: i2c@2060000 {
-		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
-		reg = <0x0 0x2060000 0x0 0x100>;
-		interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clock-names = "fck";
-		clocks = <&k3_clks 193 0>;
-		power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
-	};
+	// main_uart1: serial@2810000 {
+	// 	compatible = "ti,j721e-uart", "ti,am654-uart";
+	// 	reg = <0x00 0x02810000 0x00 0x100>;
+	// 	reg-shift = <2>;
+	// 	reg-io-width = <4>;
+	// 	interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+	// 	clock-frequency = <48000000>;
+	// 	current-speed = <115200>;
+	// 	power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 278 0>;
+	// 	clock-names = "fclk";
+	// };
+
+	// main_uart2: serial@2820000 {
+	// 	compatible = "ti,j721e-uart", "ti,am654-uart";
+	// 	reg = <0x00 0x02820000 0x00 0x100>;
+	// 	reg-shift = <2>;
+	// 	reg-io-width = <4>;
+	// 	interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+	// 	clock-frequency = <48000000>;
+	// 	current-speed = <115200>;
+	// 	power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 279 0>;
+	// 	clock-names = "fclk";
+	// };
+
+	// main_uart3: serial@2830000 {
+	// 	compatible = "ti,j721e-uart", "ti,am654-uart";
+	// 	reg = <0x00 0x02830000 0x00 0x100>;
+	// 	reg-shift = <2>;
+	// 	reg-io-width = <4>;
+	// 	interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
+	// 	clock-frequency = <48000000>;
+	// 	current-speed = <115200>;
+	// 	power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 280 0>;
+	// 	clock-names = "fclk";
+	// };
+
+	// main_uart4: serial@2840000 {
+	// 	compatible = "ti,j721e-uart", "ti,am654-uart";
+	// 	reg = <0x00 0x02840000 0x00 0x100>;
+	// 	reg-shift = <2>;
+	// 	reg-io-width = <4>;
+	// 	interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
+	// 	clock-frequency = <48000000>;
+	// 	current-speed = <115200>;
+	// 	power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 281 0>;
+	// 	clock-names = "fclk";
+	// };
+
+	// main_uart5: serial@2850000 {
+	// 	compatible = "ti,j721e-uart", "ti,am654-uart";
+	// 	reg = <0x00 0x02850000 0x00 0x100>;
+	// 	reg-shift = <2>;
+	// 	reg-io-width = <4>;
+	// 	interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+	// 	clock-frequency = <48000000>;
+	// 	current-speed = <115200>;
+	// 	power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 282 0>;
+	// 	clock-names = "fclk";
+	// };
+
+	// main_uart6: serial@2860000 {
+	// 	compatible = "ti,j721e-uart", "ti,am654-uart";
+	// 	reg = <0x00 0x02860000 0x00 0x100>;
+	// 	reg-shift = <2>;
+	// 	reg-io-width = <4>;
+	// 	interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
+	// 	clock-frequency = <48000000>;
+	// 	current-speed = <115200>;
+	// 	power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 283 0>;
+	// 	clock-names = "fclk";
+	// };
+
+	// main_uart7: serial@2870000 {
+	// 	compatible = "ti,j721e-uart", "ti,am654-uart";
+	// 	reg = <0x00 0x02870000 0x00 0x100>;
+	// 	reg-shift = <2>;
+	// 	reg-io-width = <4>;
+	// 	interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+	// 	clock-frequency = <48000000>;
+	// 	current-speed = <115200>;
+	// 	power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 284 0>;
+	// 	clock-names = "fclk";
+	// };
+
+	// main_uart8: serial@2880000 {
+	// 	compatible = "ti,j721e-uart", "ti,am654-uart";
+	// 	reg = <0x00 0x02880000 0x00 0x100>;
+	// 	reg-shift = <2>;
+	// 	reg-io-width = <4>;
+	// 	interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
+	// 	clock-frequency = <48000000>;
+	// 	current-speed = <115200>;
+	// 	power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 285 0>;
+	// 	clock-names = "fclk";
+	// };
+
+	// main_uart9: serial@2890000 {
+	// 	compatible = "ti,j721e-uart", "ti,am654-uart";
+	// 	reg = <0x00 0x02890000 0x00 0x100>;
+	// 	reg-shift = <2>;
+	// 	reg-io-width = <4>;
+	// 	interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
+	// 	clock-frequency = <48000000>;
+	// 	current-speed = <115200>;
+	// 	power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 286 0>;
+	// 	clock-names = "fclk";
+	// };
+
+	// main_gpio0: gpio@600000 {
+	// 	compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+	// 	reg = <0x0 0x00600000 0x0 0x100>;
+	// 	gpio-controller;
+	// 	#gpio-cells = <2>;
+	// 	interrupt-parent = <&main_gpio_intr>;
+	// 	interrupts = <256>, <257>, <258>, <259>,
+	// 		     <260>, <261>, <262>, <263>;
+	// 	interrupt-controller;
+	// 	#interrupt-cells = <2>;
+	// 	ti,ngpio = <128>;
+	// 	ti,davinci-gpio-unbanked = <0>;
+	// 	power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 105 0>;
+	// 	clock-names = "gpio";
+	// };
+
+	// main_gpio1: gpio@601000 {
+	// 	compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+	// 	reg = <0x0 0x00601000 0x0 0x100>;
+	// 	gpio-controller;
+	// 	#gpio-cells = <2>;
+	// 	interrupt-parent = <&main_gpio_intr>;
+	// 	interrupts = <288>, <289>, <290>;
+	// 	interrupt-controller;
+	// 	#interrupt-cells = <2>;
+	// 	ti,ngpio = <36>;
+	// 	ti,davinci-gpio-unbanked = <0>;
+	// 	power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 106 0>;
+	// 	clock-names = "gpio";
+	// };
+
+	// main_gpio2: gpio@610000 {
+	// 	compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+	// 	reg = <0x0 0x00610000 0x0 0x100>;
+	// 	gpio-controller;
+	// 	#gpio-cells = <2>;
+	// 	interrupt-parent = <&main_gpio_intr>;
+	// 	interrupts = <264>, <265>, <266>, <267>,
+	// 		     <268>, <269>, <270>, <271>;
+	// 	interrupt-controller;
+	// 	#interrupt-cells = <2>;
+	// 	ti,ngpio = <128>;
+	// 	ti,davinci-gpio-unbanked = <0>;
+	// 	power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 107 0>;
+	// 	clock-names = "gpio";
+	// };
+
+	// main_gpio3: gpio@611000 {
+	// 	compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+	// 	reg = <0x0 0x00611000 0x0 0x100>;
+	// 	gpio-controller;
+	// 	#gpio-cells = <2>;
+	// 	interrupt-parent = <&main_gpio_intr>;
+	// 	interrupts = <292>, <293>, <294>;
+	// 	interrupt-controller;
+	// 	#interrupt-cells = <2>;
+	// 	ti,ngpio = <36>;
+	// 	ti,davinci-gpio-unbanked = <0>;
+	// 	power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 108 0>;
+	// 	clock-names = "gpio";
+	// };
+
+	// main_gpio4: gpio@620000 {
+	// 	compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+	// 	reg = <0x0 0x00620000 0x0 0x100>;
+	// 	gpio-controller;
+	// 	#gpio-cells = <2>;
+	// 	interrupt-parent = <&main_gpio_intr>;
+	// 	interrupts = <272>, <273>, <274>, <275>,
+	// 		     <276>, <277>, <278>, <279>;
+	// 	interrupt-controller;
+	// 	#interrupt-cells = <2>;
+	// 	ti,ngpio = <128>;
+	// 	ti,davinci-gpio-unbanked = <0>;
+	// 	power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 109 0>;
+	// 	clock-names = "gpio";
+	// };
+
+	// main_gpio5: gpio@621000 {
+	// 	compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+	// 	reg = <0x0 0x00621000 0x0 0x100>;
+	// 	gpio-controller;
+	// 	#gpio-cells = <2>;
+	// 	interrupt-parent = <&main_gpio_intr>;
+	// 	interrupts = <296>, <297>, <298>;
+	// 	interrupt-controller;
+	// 	#interrupt-cells = <2>;
+	// 	ti,ngpio = <36>;
+	// 	ti,davinci-gpio-unbanked = <0>;
+	// 	power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 110 0>;
+	// 	clock-names = "gpio";
+	// };
+
+	// main_gpio6: gpio@630000 {
+	// 	compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+	// 	reg = <0x0 0x00630000 0x0 0x100>;
+	// 	gpio-controller;
+	// 	#gpio-cells = <2>;
+	// 	interrupt-parent = <&main_gpio_intr>;
+	// 	interrupts = <280>, <281>, <282>, <283>,
+	// 		     <284>, <285>, <286>, <287>;
+	// 	interrupt-controller;
+	// 	#interrupt-cells = <2>;
+	// 	ti,ngpio = <128>;
+	// 	ti,davinci-gpio-unbanked = <0>;
+	// 	power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 111 0>;
+	// 	clock-names = "gpio";
+	// };
+
+	// main_gpio7: gpio@631000 {
+	// 	compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+	// 	reg = <0x0 0x00631000 0x0 0x100>;
+	// 	gpio-controller;
+	// 	#gpio-cells = <2>;
+	// 	interrupt-parent = <&main_gpio_intr>;
+	// 	interrupts = <300>, <301>, <302>;
+	// 	interrupt-controller;
+	// 	#interrupt-cells = <2>;
+	// 	ti,ngpio = <36>;
+	// 	ti,davinci-gpio-unbanked = <0>;
+	// 	power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 112 0>;
+	// 	clock-names = "gpio";
+	// };
+
+	// main_rti0: watchdog@2200000 {
+	// 	compatible = "ti,rti-wdt";
+	// 	reg = <0x0 0x2200000 0x0 0x100>;
+	// 	clocks = <&k3_clks 252 1>;
+	// 	power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
+	// 	assigned-clocks = <&k3_clks 252 1>;
+	// 	assigned-clock-parents = <&k3_clks 252 5>;
+	// };
+
+	// main_rti1: watchdog@2210000 {
+	// 	compatible = "ti,rti-wdt";
+	// 	reg = <0x0 0x2210000 0x0 0x100>;
+	// 	clocks = <&k3_clks 253 1>;
+	// 	power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
+	// 	assigned-clocks = <&k3_clks 253 1>;
+	// 	assigned-clock-parents = <&k3_clks 253 5>;
+	// };
+
+	// main_i2c0: i2c@2000000 {
+	// 	compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+	// 	reg = <0x0 0x2000000 0x0 0x100>;
+	// 	interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
+	// 	#address-cells = <1>;
+	// 	#size-cells = <0>;
+	// 	clock-names = "fck";
+	// 	clocks = <&k3_clks 187 0>;
+	// 	power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
+	// };
+
+	// main_i2c1: i2c@2010000 {
+	// 	compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+	// 	reg = <0x0 0x2010000 0x0 0x100>;
+	// 	interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
+	// 	#address-cells = <1>;
+	// 	#size-cells = <0>;
+	// 	clock-names = "fck";
+	// 	clocks = <&k3_clks 188 0>;
+	// 	power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
+	// };
+
+	// main_i2c2: i2c@2020000 {
+	// 	compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+	// 	reg = <0x0 0x2020000 0x0 0x100>;
+	// 	interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
+	// 	#address-cells = <1>;
+	// 	#size-cells = <0>;
+	// 	clock-names = "fck";
+	// 	clocks = <&k3_clks 189 0>;
+	// 	power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
+	// };
+
+	// main_i2c3: i2c@2030000 {
+	// 	compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+	// 	reg = <0x0 0x2030000 0x0 0x100>;
+	// 	interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
+	// 	#address-cells = <1>;
+	// 	#size-cells = <0>;
+	// 	clock-names = "fck";
+	// 	clocks = <&k3_clks 190 0>;
+	// 	power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
+	// };
+
+	// main_i2c4: i2c@2040000 {
+	// 	compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+	// 	reg = <0x0 0x2040000 0x0 0x100>;
+	// 	interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
+	// 	#address-cells = <1>;
+	// 	#size-cells = <0>;
+	// 	clock-names = "fck";
+	// 	clocks = <&k3_clks 191 0>;
+	// 	power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
+	// };
+
+	// main_i2c5: i2c@2050000 {
+	// 	compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+	// 	reg = <0x0 0x2050000 0x0 0x100>;
+	// 	interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+	// 	#address-cells = <1>;
+	// 	#size-cells = <0>;
+	// 	clock-names = "fck";
+	// 	clocks = <&k3_clks 192 0>;
+	// 	power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
+	// };
+
+	// main_i2c6: i2c@2060000 {
+	// 	compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+	// 	reg = <0x0 0x2060000 0x0 0x100>;
+	// 	interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
+	// 	#address-cells = <1>;
+	// 	#size-cells = <0>;
+	// 	clock-names = "fck";
+	// 	clocks = <&k3_clks 193 0>;
+	// 	power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
+	// };
 
 	ufs_wrapper: ufs-wrapper@4e80000 {
 		compatible = "ti,j721e-ufs";
@@ -1373,233 +1373,233 @@
 		clock-names = "ctrl";
 	};
 
-	mcasp0: mcasp@02b00000 {
-		compatible = "ti,am33xx-mcasp-audio";
-		reg = <0x0 0x02b00000 0x0 0x2000>,
-			<0x0 0x02b08000 0x0 0x1000>;
-		reg-names = "mpu","dat";
-		interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "tx", "rx";
-
-		dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
-		dma-names = "tx", "rx";
-
-		clocks = <&k3_clks 174 1>;
-		clock-names = "fck";
-		power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>;
-
-		status = "disabled";
-	};
-
-	mcasp1: mcasp@02b10000 {
-		compatible = "ti,am33xx-mcasp-audio";
-		reg = <0x0 0x02b10000 0x0 0x2000>,
-			<0x0 0x02b18000 0x0 0x1000>;
-		reg-names = "mpu","dat";
-		interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "tx", "rx";
-
-		dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
-		dma-names = "tx", "rx";
-
-		clocks = <&k3_clks 175 1>;
-		clock-names = "fck";
-		power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>;
-
-		status = "disabled";
-	};
-
-	mcasp2: mcasp@02b20000 {
-		compatible = "ti,am33xx-mcasp-audio";
-		reg = <0x0 0x02b20000 0x0 0x2000>,
-			<0x0 0x02b28000 0x0 0x1000>;
-		reg-names = "mpu","dat";
-		interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "tx", "rx";
-
-		dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
-		dma-names = "tx", "rx";
-
-		clocks = <&k3_clks 176 1>;
-		clock-names = "fck";
-		power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>;
-
-		status = "disabled";
-	};
-
-	mcasp3: mcasp@02b30000 {
-		compatible = "ti,am33xx-mcasp-audio";
-		reg = <0x0 0x02b30000 0x0 0x2000>,
-			<0x0 0x02b38000 0x0 0x1000>;
-		reg-names = "mpu","dat";
-		interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "tx", "rx";
-
-		dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
-		dma-names = "tx", "rx";
-
-		clocks = <&k3_clks 177 1>;
-		clock-names = "fck";
-		power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>;
-
-		status = "disabled";
-	};
-
-	mcasp4: mcasp@02b40000 {
-		compatible = "ti,am33xx-mcasp-audio";
-		reg = <0x0 0x02b40000 0x0 0x2000>,
-			<0x0 0x02b48000 0x0 0x1000>;
-		reg-names = "mpu","dat";
-		interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "tx", "rx";
-
-		dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>;
-		dma-names = "tx", "rx";
-
-		clocks = <&k3_clks 178 1>;
-		clock-names = "fck";
-		power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
-
-		status = "disabled";
-	};
-
-	mcasp5: mcasp@02b50000 {
-		compatible = "ti,am33xx-mcasp-audio";
-		reg = <0x0 0x02b50000 0x0 0x2000>,
-			<0x0 0x02b58000 0x0 0x1000>;
-		reg-names = "mpu","dat";
-		interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "tx", "rx";
-
-		dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>;
-		dma-names = "tx", "rx";
-
-		clocks = <&k3_clks 179 1>;
-		clock-names = "fck";
-		power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
-
-		status = "disabled";
-	};
-
-	mcasp6: mcasp@02b60000 {
-		compatible = "ti,am33xx-mcasp-audio";
-		reg = <0x0 0x02b60000 0x0 0x2000>,
-			<0x0 0x02b68000 0x0 0x1000>;
-		reg-names = "mpu","dat";
-		interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "tx", "rx";
-
-		dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>;
-		dma-names = "tx", "rx";
-
-		clocks = <&k3_clks 180 1>;
-		clock-names = "fck";
-		power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>;
-
-		status = "disabled";
-	};
-
-	mcasp7: mcasp@02b70000 {
-		compatible = "ti,am33xx-mcasp-audio";
-		reg = <0x0 0x02b70000 0x0 0x2000>,
-			<0x0 0x02b78000 0x0 0x1000>;
-		reg-names = "mpu","dat";
-		interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "tx", "rx";
-
-		dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>;
-		dma-names = "tx", "rx";
-
-		clocks = <&k3_clks 181 1>;
-		clock-names = "fck";
-		power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>;
-
-		status = "disabled";
-	};
-
-	mcasp8: mcasp@02b80000 {
-		compatible = "ti,am33xx-mcasp-audio";
-		reg = <0x0 0x02b80000 0x0 0x2000>,
-			<0x0 0x02b88000 0x0 0x1000>;
-		reg-names = "mpu","dat";
-		interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "tx", "rx";
-
-		dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>;
-		dma-names = "tx", "rx";
-
-		clocks = <&k3_clks 182 1>;
-		clock-names = "fck";
-		power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
-
-		status = "disabled";
-	};
-
-	mcasp9: mcasp@02b90000 {
-		compatible = "ti,am33xx-mcasp-audio";
-		reg = <0x0 0x02b90000 0x0 0x2000>,
-			<0x0 0x02b98000 0x0 0x1000>;
-		reg-names = "mpu","dat";
-		interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "tx", "rx";
-
-		dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>;
-		dma-names = "tx", "rx";
-
-		clocks = <&k3_clks 183 1>;
-		clock-names = "fck";
-		power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
-
-		status = "disabled";
-	};
-
-	mcasp10: mcasp@02ba0000 {
-		compatible = "ti,am33xx-mcasp-audio";
-		reg = <0x0 0x02ba0000 0x0 0x2000>,
-			<0x0 0x02ba8000 0x0 0x1000>;
-		reg-names = "mpu","dat";
-		interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "tx", "rx";
-
-		dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>;
-		dma-names = "tx", "rx";
-
-		clocks = <&k3_clks 184 1>;
-		clock-names = "fck";
-		power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
-
-		status = "disabled";
-	};
-
-	mcasp11: mcasp@02bb0000 {
-		compatible = "ti,am33xx-mcasp-audio";
-		reg = <0x0 0x02bb0000 0x0 0x2000>,
-			<0x0 0x02bb8000 0x0 0x1000>;
-		reg-names = "mpu","dat";
-		interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "tx", "rx";
-
-		dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>;
-		dma-names = "tx", "rx";
-
-		clocks = <&k3_clks 185 1>;
-		clock-names = "fck";
-		power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
-
-		status = "disabled";
-	};
+	// mcasp0: mcasp@02b00000 {
+	// 	compatible = "ti,am33xx-mcasp-audio";
+	// 	reg = <0x0 0x02b00000 0x0 0x2000>,
+	// 		<0x0 0x02b08000 0x0 0x1000>;
+	// 	reg-names = "mpu","dat";
+	// 	interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
+	// 			<GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
+	// 	interrupt-names = "tx", "rx";
+
+	// 	dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
+	// 	dma-names = "tx", "rx";
+
+	// 	clocks = <&k3_clks 174 1>;
+	// 	clock-names = "fck";
+	// 	power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>;
+
+	// 	status = "disabled";
+	// };
+
+	// mcasp1: mcasp@02b10000 {
+	// 	compatible = "ti,am33xx-mcasp-audio";
+	// 	reg = <0x0 0x02b10000 0x0 0x2000>,
+	// 		<0x0 0x02b18000 0x0 0x1000>;
+	// 	reg-names = "mpu","dat";
+	// 	interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>,
+	// 			<GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>;
+	// 	interrupt-names = "tx", "rx";
+
+	// 	dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
+	// 	dma-names = "tx", "rx";
+
+	// 	clocks = <&k3_clks 175 1>;
+	// 	clock-names = "fck";
+	// 	power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>;
+
+	// 	status = "disabled";
+	// };
+
+	// mcasp2: mcasp@02b20000 {
+	// 	compatible = "ti,am33xx-mcasp-audio";
+	// 	reg = <0x0 0x02b20000 0x0 0x2000>,
+	// 		<0x0 0x02b28000 0x0 0x1000>;
+	// 	reg-names = "mpu","dat";
+	// 	interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>,
+	// 			<GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>;
+	// 	interrupt-names = "tx", "rx";
+
+	// 	dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
+	// 	dma-names = "tx", "rx";
+
+	// 	clocks = <&k3_clks 176 1>;
+	// 	clock-names = "fck";
+	// 	power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>;
+
+	// 	status = "disabled";
+	// };
+
+	// mcasp3: mcasp@02b30000 {
+	// 	compatible = "ti,am33xx-mcasp-audio";
+	// 	reg = <0x0 0x02b30000 0x0 0x2000>,
+	// 		<0x0 0x02b38000 0x0 0x1000>;
+	// 	reg-names = "mpu","dat";
+	// 	interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>,
+	// 			<GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
+	// 	interrupt-names = "tx", "rx";
+
+	// 	dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
+	// 	dma-names = "tx", "rx";
+
+	// 	clocks = <&k3_clks 177 1>;
+	// 	clock-names = "fck";
+	// 	power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>;
+
+	// 	status = "disabled";
+	// };
+
+	// mcasp4: mcasp@02b40000 {
+	// 	compatible = "ti,am33xx-mcasp-audio";
+	// 	reg = <0x0 0x02b40000 0x0 0x2000>,
+	// 		<0x0 0x02b48000 0x0 0x1000>;
+	// 	reg-names = "mpu","dat";
+	// 	interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>,
+	// 			<GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
+	// 	interrupt-names = "tx", "rx";
+
+	// 	dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>;
+	// 	dma-names = "tx", "rx";
+
+	// 	clocks = <&k3_clks 178 1>;
+	// 	clock-names = "fck";
+	// 	power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
+
+	// 	status = "disabled";
+	// };
+
+	// mcasp5: mcasp@02b50000 {
+	// 	compatible = "ti,am33xx-mcasp-audio";
+	// 	reg = <0x0 0x02b50000 0x0 0x2000>,
+	// 		<0x0 0x02b58000 0x0 0x1000>;
+	// 	reg-names = "mpu","dat";
+	// 	interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>,
+	// 			<GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>;
+	// 	interrupt-names = "tx", "rx";
+
+	// 	dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>;
+	// 	dma-names = "tx", "rx";
+
+	// 	clocks = <&k3_clks 179 1>;
+	// 	clock-names = "fck";
+	// 	power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
+
+	// 	status = "disabled";
+	// };
+
+	// mcasp6: mcasp@02b60000 {
+	// 	compatible = "ti,am33xx-mcasp-audio";
+	// 	reg = <0x0 0x02b60000 0x0 0x2000>,
+	// 		<0x0 0x02b68000 0x0 0x1000>;
+	// 	reg-names = "mpu","dat";
+	// 	interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>,
+	// 			<GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>;
+	// 	interrupt-names = "tx", "rx";
+
+	// 	dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>;
+	// 	dma-names = "tx", "rx";
+
+	// 	clocks = <&k3_clks 180 1>;
+	// 	clock-names = "fck";
+	// 	power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>;
+
+	// 	status = "disabled";
+	// };
+
+	// mcasp7: mcasp@02b70000 {
+	// 	compatible = "ti,am33xx-mcasp-audio";
+	// 	reg = <0x0 0x02b70000 0x0 0x2000>,
+	// 		<0x0 0x02b78000 0x0 0x1000>;
+	// 	reg-names = "mpu","dat";
+	// 	interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>,
+	// 			<GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>;
+	// 	interrupt-names = "tx", "rx";
+
+	// 	dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>;
+	// 	dma-names = "tx", "rx";
+
+	// 	clocks = <&k3_clks 181 1>;
+	// 	clock-names = "fck";
+	// 	power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>;
+
+	// 	status = "disabled";
+	// };
+
+	// mcasp8: mcasp@02b80000 {
+	// 	compatible = "ti,am33xx-mcasp-audio";
+	// 	reg = <0x0 0x02b80000 0x0 0x2000>,
+	// 		<0x0 0x02b88000 0x0 0x1000>;
+	// 	reg-names = "mpu","dat";
+	// 	interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>,
+	// 			<GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
+	// 	interrupt-names = "tx", "rx";
+
+	// 	dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>;
+	// 	dma-names = "tx", "rx";
+
+	// 	clocks = <&k3_clks 182 1>;
+	// 	clock-names = "fck";
+	// 	power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
+
+	// 	status = "disabled";
+	// };
+
+	// mcasp9: mcasp@02b90000 {
+	// 	compatible = "ti,am33xx-mcasp-audio";
+	// 	reg = <0x0 0x02b90000 0x0 0x2000>,
+	// 		<0x0 0x02b98000 0x0 0x1000>;
+	// 	reg-names = "mpu","dat";
+	// 	interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>,
+	// 			<GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>;
+	// 	interrupt-names = "tx", "rx";
+
+	// 	dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>;
+	// 	dma-names = "tx", "rx";
+
+	// 	clocks = <&k3_clks 183 1>;
+	// 	clock-names = "fck";
+	// 	power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
+
+	// 	status = "disabled";
+	// };
+
+	// mcasp10: mcasp@02ba0000 {
+	// 	compatible = "ti,am33xx-mcasp-audio";
+	// 	reg = <0x0 0x02ba0000 0x0 0x2000>,
+	// 		<0x0 0x02ba8000 0x0 0x1000>;
+	// 	reg-names = "mpu","dat";
+	// 	interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>,
+	// 			<GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
+	// 	interrupt-names = "tx", "rx";
+
+	// 	dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>;
+	// 	dma-names = "tx", "rx";
+
+	// 	clocks = <&k3_clks 184 1>;
+	// 	clock-names = "fck";
+	// 	power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
+
+	// 	status = "disabled";
+	// };
+
+	// mcasp11: mcasp@02bb0000 {
+	// 	compatible = "ti,am33xx-mcasp-audio";
+	// 	reg = <0x0 0x02bb0000 0x0 0x2000>,
+	// 		<0x0 0x02bb8000 0x0 0x1000>;
+	// 	reg-names = "mpu","dat";
+	// 	interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>,
+	// 			<GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>;
+	// 	interrupt-names = "tx", "rx";
+
+	// 	dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>;
+	// 	dma-names = "tx", "rx";
+
+	// 	clocks = <&k3_clks 185 1>;
+	// 	clock-names = "fck";
+	// 	power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
+
+	// 	status = "disabled";
+	// };
 
 	main_sdhci0: sdhci@4f80000 {
 		compatible = "ti,j721e-sdhci-8bit";
@@ -1613,10 +1613,10 @@
 		bus-width = <8>;
 		mmc-ddr-1_8v;
 		ti,otap-del-sel-legacy = <0x0>;
-		ti,otap-del-sel-mmc-hs = <0x0>;
-		ti,otap-del-sel-ddr52 = <0x5>;
-		ti,otap-del-sel-hs200 = <0x6>;
-		ti,otap-del-sel-hs400 = <0x0>;
+		// ti,otap-del-sel-mmc-hs = <0x0>;
+		// ti,otap-del-sel-ddr52 = <0x5>;
+		// ti,otap-del-sel-hs200 = <0x6>;
+		// ti,otap-del-sel-hs400 = <0x0>;
 		ti,trm-icp = <0x8>;
 		ti,strobe-sel = <0x77>;
 		dma-coherent;
@@ -1632,39 +1632,39 @@
 		assigned-clocks = <&k3_clks 92 0>;
 		assigned-clock-parents = <&k3_clks 92 1>;
 		ti,otap-del-sel-legacy = <0x0>;
-		ti,otap-del-sel-sd-hs = <0xf>;
-		ti,otap-del-sel-sdr12 = <0xf>;
-		ti,otap-del-sel-sdr25 = <0xf>;
-		ti,otap-del-sel-sdr50 = <0xc>;
-		ti,otap-del-sel-sdr104 = <0x5>;
-		ti,otap-del-sel-ddr50 = <0xc>;
-		ti,trm-icp = <0x8>;
-		ti,clkbuf-sel = <0x7>;
-		dma-coherent;
-		sdhci-caps-mask = <0x2 0x0>;
-	};
-
-	main_sdhci2: sdhci@4f98000 {
-		compatible = "ti,j721e-sdhci-4bit";
-		reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>;
-		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
-		power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
-		clock-names = "clk_xin", "clk_ahb";
-		clocks = <&k3_clks 93 0>, <&k3_clks 93 5>;
-		assigned-clocks = <&k3_clks 93 0>;
-		assigned-clock-parents = <&k3_clks 93 1>;
-		ti,otap-del-sel-legacy = <0x0>;
-		ti,otap-del-sel-sd-hs = <0xf>;
-		ti,otap-del-sel-sdr12 = <0xf>;
-		ti,otap-del-sel-sdr25 = <0xf>;
-		ti,otap-del-sel-sdr50 = <0xc>;
-		ti,otap-del-sel-sdr104 = <0x5>;
-		ti,otap-del-sel-ddr50 = <0xc>;
+		// ti,otap-del-sel-sd-hs = <0xf>;
+		// ti,otap-del-sel-sdr12 = <0xf>;
+		// ti,otap-del-sel-sdr25 = <0xf>;
+		// ti,otap-del-sel-sdr50 = <0xc>;
+		// ti,otap-del-sel-sdr104 = <0x5>;
+		// ti,otap-del-sel-ddr50 = <0xc>;
 		ti,trm-icp = <0x8>;
 		ti,clkbuf-sel = <0x7>;
 		dma-coherent;
-		sdhci-caps-mask = <0x2 0x0>;
-	};
+		// sdhci-caps-mask = <0x2 0x0>;
+	};
+
+	// main_sdhci2: sdhci@4f98000 {
+	// 	compatible = "ti,j721e-sdhci-4bit";
+	// 	reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>;
+	// 	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+	// 	power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
+	// 	clock-names = "clk_xin", "clk_ahb";
+	// 	clocks = <&k3_clks 93 0>, <&k3_clks 93 5>;
+	// 	assigned-clocks = <&k3_clks 93 0>;
+	// 	assigned-clock-parents = <&k3_clks 93 1>;
+	// 	ti,otap-del-sel-legacy = <0x0>;
+	// 	ti,otap-del-sel-sd-hs = <0xf>;
+	// 	ti,otap-del-sel-sdr12 = <0xf>;
+	// 	ti,otap-del-sel-sdr25 = <0xf>;
+	// 	ti,otap-del-sel-sdr50 = <0xc>;
+	// 	ti,otap-del-sel-sdr104 = <0x5>;
+	// 	ti,otap-del-sel-ddr50 = <0xc>;
+	// 	ti,trm-icp = <0x8>;
+	// 	ti,clkbuf-sel = <0x7>;
+	// 	dma-coherent;
+	// 	sdhci-caps-mask = <0x2 0x0>;
+	// };
 
 	main_r5fss0: r5fss@5c00000 {
 		compatible = "ti,j721e-r5fss";
@@ -2166,260 +2166,260 @@
 		};
 	};
 
-	usbss0: cdns_usb@4104000 {
-		compatible = "ti,j721e-usb";
-		reg = <0x00 0x4104000 0x00 0x100>;
-		dma-coherent;
-		power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
-		clock-names = "ref", "lpm";
-		assigned-clocks = <&k3_clks 288 15>;	/* USB2_REFCLK */
-		assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-
-		usb0: usb@6000000 {
-			compatible = "cdns,usb3";
-			reg = <0x00 0x6000000 0x00 0x10000>,
-			      <0x00 0x6010000 0x00 0x10000>,
-			      <0x00 0x6020000 0x00 0x10000>;
-			reg-names = "otg", "xhci", "dev";
-			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,	/* irq.0 */
-				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,	/* irq.6 */
-				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;	/* otgirq.0 */
-			interrupt-names = "host",
-					  "peripheral",
-					  "otg";
-			maximum-speed = "super-speed";
-			dr_mode = "otg";
-		};
-	};
-
-	usbss1: cdns_usb@4114000 {
-		compatible = "ti,j721e-usb";
-		reg = <0x00 0x4114000 0x00 0x100>;
-		dma-coherent;
-		power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 289 15>, <&k3_clks 289 3>;
-		clock-names = "ref", "lpm";
-		assigned-clocks = <&k3_clks 289 15>;	/* USB2_REFCLK */
-		assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-
-		usb1: usb@6400000 {
-			compatible = "cdns,usb3";
-			reg = <0x00 0x6400000 0x00 0x10000>,
-			      <0x00 0x6410000 0x00 0x10000>,
-			      <0x00 0x6420000 0x00 0x10000>;
-			reg-names = "otg", "xhci", "dev";
-			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,	/* irq.0 */
-				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,	/* irq.6 */
-				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;	/* otgirq.0 */
-			interrupt-names = "host",
-					  "peripheral",
-					  "otg";
-			maximum-speed = "super-speed";
-			dr_mode = "otg";
-		};
-	};
-
-	main_mcan0: can@2701000 {
-		compatible = "bosch,m_can";
-		reg = <0x00 0x02701000 0x00 0x200>,
-		      <0x00 0x02708000 0x00 0x8000>;
-		reg-names = "m_can", "message_ram";
-		power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 156 1>, <&k3_clks 156 0>;
-		clock-names = "cclk", "hclk";
-		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "int0", "int1";
-		bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
-	};
-
-	main_mcan1: can@2711000 {
-		compatible = "bosch,m_can";
-		reg = <0x00 0x02711000 0x00 0x200>,
-		      <0x00 0x02718000 0x00 0x8000>;
-		reg-names = "m_can", "message_ram";
-		power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 158 1>, <&k3_clks 158 0>;
-		clock-names = "cclk", "hclk";
-		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "int0", "int1";
-		bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
-	};
-
-	main_mcan2: can@2721000 {
-		compatible = "bosch,m_can";
-		reg = <0x00 0x02721000 0x00 0x200>,
-		      <0x00 0x02728000 0x00 0x8000>;
-		reg-names = "m_can", "message_ram";
-		power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 160 1>, <&k3_clks 160 0>;
-		clock-names = "cclk", "hclk";
-		interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "int0", "int1";
-		bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
-	};
-
-	main_mcan3: can@2731000 {
-		compatible = "bosch,m_can";
-		reg = <0x00 0x02731000 0x00 0x200>,
-		      <0x00 0x02738000 0x00 0x8000>;
-		reg-names = "m_can", "message_ram";
-		power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 161 1>, <&k3_clks 161 0>;
-		clock-names = "cclk", "hclk";
-		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "int0", "int1";
-		bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
-	};
-
-	main_mcan4: can@2741000 {
-		compatible = "bosch,m_can";
-		reg = <0x00 0x02741000 0x00 0x200>,
-		      <0x00 0x02748000 0x00 0x8000>;
-		reg-names = "m_can", "message_ram";
-		power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 162 1>, <&k3_clks 162 0>;
-		clock-names = "cclk", "hclk";
-		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "int0", "int1";
-		bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
-	};
-
-	main_mcan5: can@2751000 {
-		compatible = "bosch,m_can";
-		reg = <0x00 0x02751000 0x00 0x200>,
-		      <0x00 0x02758000 0x00 0x8000>;
-		reg-names = "m_can", "message_ram";
-		power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 163 1>, <&k3_clks 163 0>;
-		clock-names = "cclk", "hclk";
-		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "int0", "int1";
-		bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
-	};
-
-	main_mcan6: can@2761000 {
-		compatible = "bosch,m_can";
-		reg = <0x00 0x02761000 0x00 0x200>,
-		      <0x00 0x02768000 0x00 0x8000>;
-		reg-names = "m_can", "message_ram";
-		power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 164 1>, <&k3_clks 164 0>;
-		clock-names = "cclk", "hclk";
-		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "int0", "int1";
-		bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
-	};
-
-	main_mcan7: can@2771000 {
-		compatible = "bosch,m_can";
-		reg = <0x00 0x02771000 0x00 0x200>,
-		      <0x00 0x02778000 0x00 0x8000>;
-		reg-names = "m_can", "message_ram";
-		power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 165 1>, <&k3_clks 165 0>;
-		clock-names = "cclk", "hclk";
-		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "int0", "int1";
-		bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
-	};
-
-	main_mcan8: can@2781000 {
-		compatible = "bosch,m_can";
-		reg = <0x00 0x02781000 0x00 0x200>,
-		      <0x00 0x02788000 0x00 0x8000>;
-		reg-names = "m_can", "message_ram";
-		power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 166 1>, <&k3_clks 166 0>;
-		clock-names = "cclk", "hclk";
-		interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "int0", "int1";
-		bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
-	};
-
-	main_mcan9: can@2791000 {
-		compatible = "bosch,m_can";
-		reg = <0x00 0x02791000 0x00 0x200>,
-		      <0x00 0x02798000 0x00 0x8000>;
-		reg-names = "m_can", "message_ram";
-		power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 167 1>, <&k3_clks 167 0>;
-		clock-names = "cclk", "hclk";
-		interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "int0", "int1";
-		bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
-	};
-
-	main_mcan10: can@27a1000 {
-		compatible = "bosch,m_can";
-		reg = <0x00 0x027a1000 0x00 0x200>,
-		      <0x00 0x027a8000 0x00 0x8000>;
-		reg-names = "m_can", "message_ram";
-		power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 168 1>, <&k3_clks 168 0>;
-		clock-names = "cclk", "hclk";
-		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "int0", "int1";
-		bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
-	};
-
-	main_mcan11: can@27b1000 {
-		compatible = "bosch,m_can";
-		reg = <0x00 0x027b1000 0x00 0x200>,
-		      <0x00 0x027b8000 0x00 0x8000>;
-		reg-names = "m_can", "message_ram";
-		power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 169 1>, <&k3_clks 169 0>;
-		clock-names = "cclk", "hclk";
-		interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "int0", "int1";
-		bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
-	};
-
-	main_mcan12: can@27c1000 {
-		compatible = "bosch,m_can";
-		reg = <0x00 0x027c1000 0x00 0x200>,
-		      <0x00 0x027c8000 0x00 0x8000>;
-		reg-names = "m_can", "message_ram";
-		power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 170 1>, <&k3_clks 170 0>;
-		clock-names = "cclk", "hclk";
-		interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "int0", "int1";
-		bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
-	};
-
-	main_mcan13: can@27d1000 {
-		compatible = "bosch,m_can";
-		reg = <0x00 0x027d1000 0x00 0x200>,
-		      <0x00 0x027d8000 0x00 0x8000>;
-		reg-names = "m_can", "message_ram";
-		power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 171 1>, <&k3_clks 171 0>;
-		clock-names = "cclk", "hclk";
-		interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "int0", "int1";
-		bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
-	};
+	// usbss0: cdns_usb@4104000 {
+	// 	compatible = "ti,j721e-usb";
+	// 	reg = <0x00 0x4104000 0x00 0x100>;
+	// 	dma-coherent;
+	// 	power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
+	// 	clock-names = "ref", "lpm";
+	// 	assigned-clocks = <&k3_clks 288 15>;	/* USB2_REFCLK */
+	// 	assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
+	// 	#address-cells = <2>;
+	// 	#size-cells = <2>;
+	// 	ranges;
+
+	// 	usb0: usb@6000000 {
+	// 		compatible = "cdns,usb3";
+	// 		reg = <0x00 0x6000000 0x00 0x10000>,
+	// 		      <0x00 0x6010000 0x00 0x10000>,
+	// 		      <0x00 0x6020000 0x00 0x10000>;
+	// 		reg-names = "otg", "xhci", "dev";
+	// 		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,	/* irq.0 */
+	// 			     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,	/* irq.6 */
+	// 			     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;	/* otgirq.0 */
+	// 		interrupt-names = "host",
+	// 				  "peripheral",
+	// 				  "otg";
+	// 		maximum-speed = "super-speed";
+	// 		dr_mode = "otg";
+	// 	};
+	// };
+
+	// usbss1: cdns_usb@4114000 {
+	// 	compatible = "ti,j721e-usb";
+	// 	reg = <0x00 0x4114000 0x00 0x100>;
+	// 	dma-coherent;
+	// 	power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 289 15>, <&k3_clks 289 3>;
+	// 	clock-names = "ref", "lpm";
+	// 	assigned-clocks = <&k3_clks 289 15>;	/* USB2_REFCLK */
+	// 	assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
+	// 	#address-cells = <2>;
+	// 	#size-cells = <2>;
+	// 	ranges;
+
+	// 	usb1: usb@6400000 {
+	// 		compatible = "cdns,usb3";
+	// 		reg = <0x00 0x6400000 0x00 0x10000>,
+	// 		      <0x00 0x6410000 0x00 0x10000>,
+	// 		      <0x00 0x6420000 0x00 0x10000>;
+	// 		reg-names = "otg", "xhci", "dev";
+	// 		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,	/* irq.0 */
+	// 			     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,	/* irq.6 */
+	// 			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;	/* otgirq.0 */
+	// 		interrupt-names = "host",
+	// 				  "peripheral",
+	// 				  "otg";
+	// 		maximum-speed = "super-speed";
+	// 		dr_mode = "otg";
+	// 	};
+	// };
+
+	// main_mcan0: can@2701000 {
+	// 	compatible = "bosch,m_can";
+	// 	reg = <0x00 0x02701000 0x00 0x200>,
+	// 	      <0x00 0x02708000 0x00 0x8000>;
+	// 	reg-names = "m_can", "message_ram";
+	// 	power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 156 1>, <&k3_clks 156 0>;
+	// 	clock-names = "cclk", "hclk";
+	// 	interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+	// 		     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+	// 	interrupt-names = "int0", "int1";
+	// 	bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
+	// };
+
+	// main_mcan1: can@2711000 {
+	// 	compatible = "bosch,m_can";
+	// 	reg = <0x00 0x02711000 0x00 0x200>,
+	// 	      <0x00 0x02718000 0x00 0x8000>;
+	// 	reg-names = "m_can", "message_ram";
+	// 	power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 158 1>, <&k3_clks 158 0>;
+	// 	clock-names = "cclk", "hclk";
+	// 	interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+	// 		     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+	// 	interrupt-names = "int0", "int1";
+	// 	bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
+	// };
+
+	// main_mcan2: can@2721000 {
+	// 	compatible = "bosch,m_can";
+	// 	reg = <0x00 0x02721000 0x00 0x200>,
+	// 	      <0x00 0x02728000 0x00 0x8000>;
+	// 	reg-names = "m_can", "message_ram";
+	// 	power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 160 1>, <&k3_clks 160 0>;
+	// 	clock-names = "cclk", "hclk";
+	// 	interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+	// 		     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+	// 	interrupt-names = "int0", "int1";
+	// 	bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
+	// };
+
+	// main_mcan3: can@2731000 {
+	// 	compatible = "bosch,m_can";
+	// 	reg = <0x00 0x02731000 0x00 0x200>,
+	// 	      <0x00 0x02738000 0x00 0x8000>;
+	// 	reg-names = "m_can", "message_ram";
+	// 	power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 161 1>, <&k3_clks 161 0>;
+	// 	clock-names = "cclk", "hclk";
+	// 	interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+	// 		     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+	// 	interrupt-names = "int0", "int1";
+	// 	bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
+	// };
+
+	// main_mcan4: can@2741000 {
+	// 	compatible = "bosch,m_can";
+	// 	reg = <0x00 0x02741000 0x00 0x200>,
+	// 	      <0x00 0x02748000 0x00 0x8000>;
+	// 	reg-names = "m_can", "message_ram";
+	// 	power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 162 1>, <&k3_clks 162 0>;
+	// 	clock-names = "cclk", "hclk";
+	// 	interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+	// 		     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+	// 	interrupt-names = "int0", "int1";
+	// 	bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
+	// };
+
+	// main_mcan5: can@2751000 {
+	// 	compatible = "bosch,m_can";
+	// 	reg = <0x00 0x02751000 0x00 0x200>,
+	// 	      <0x00 0x02758000 0x00 0x8000>;
+	// 	reg-names = "m_can", "message_ram";
+	// 	power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 163 1>, <&k3_clks 163 0>;
+	// 	clock-names = "cclk", "hclk";
+	// 	interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+	// 		     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+	// 	interrupt-names = "int0", "int1";
+	// 	bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
+	// };
+
+	// main_mcan6: can@2761000 {
+	// 	compatible = "bosch,m_can";
+	// 	reg = <0x00 0x02761000 0x00 0x200>,
+	// 	      <0x00 0x02768000 0x00 0x8000>;
+	// 	reg-names = "m_can", "message_ram";
+	// 	power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 164 1>, <&k3_clks 164 0>;
+	// 	clock-names = "cclk", "hclk";
+	// 	interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+	// 		     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+	// 	interrupt-names = "int0", "int1";
+	// 	bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
+	// };
+
+	// main_mcan7: can@2771000 {
+	// 	compatible = "bosch,m_can";
+	// 	reg = <0x00 0x02771000 0x00 0x200>,
+	// 	      <0x00 0x02778000 0x00 0x8000>;
+	// 	reg-names = "m_can", "message_ram";
+	// 	power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 165 1>, <&k3_clks 165 0>;
+	// 	clock-names = "cclk", "hclk";
+	// 	interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+	// 		     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+	// 	interrupt-names = "int0", "int1";
+	// 	bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
+	// };
+
+	// main_mcan8: can@2781000 {
+	// 	compatible = "bosch,m_can";
+	// 	reg = <0x00 0x02781000 0x00 0x200>,
+	// 	      <0x00 0x02788000 0x00 0x8000>;
+	// 	reg-names = "m_can", "message_ram";
+	// 	power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 166 1>, <&k3_clks 166 0>;
+	// 	clock-names = "cclk", "hclk";
+	// 	interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
+	// 		     <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
+	// 	interrupt-names = "int0", "int1";
+	// 	bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
+	// };
+
+	// main_mcan9: can@2791000 {
+	// 	compatible = "bosch,m_can";
+	// 	reg = <0x00 0x02791000 0x00 0x200>,
+	// 	      <0x00 0x02798000 0x00 0x8000>;
+	// 	reg-names = "m_can", "message_ram";
+	// 	power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 167 1>, <&k3_clks 167 0>;
+	// 	clock-names = "cclk", "hclk";
+	// 	interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
+	// 		     <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
+	// 	interrupt-names = "int0", "int1";
+	// 	bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
+	// };
+
+	// main_mcan10: can@27a1000 {
+	// 	compatible = "bosch,m_can";
+	// 	reg = <0x00 0x027a1000 0x00 0x200>,
+	// 	      <0x00 0x027a8000 0x00 0x8000>;
+	// 	reg-names = "m_can", "message_ram";
+	// 	power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 168 1>, <&k3_clks 168 0>;
+	// 	clock-names = "cclk", "hclk";
+	// 	interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
+	// 		     <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+	// 	interrupt-names = "int0", "int1";
+	// 	bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
+	// };
+
+	// main_mcan11: can@27b1000 {
+	// 	compatible = "bosch,m_can";
+	// 	reg = <0x00 0x027b1000 0x00 0x200>,
+	// 	      <0x00 0x027b8000 0x00 0x8000>;
+	// 	reg-names = "m_can", "message_ram";
+	// 	power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 169 1>, <&k3_clks 169 0>;
+	// 	clock-names = "cclk", "hclk";
+	// 	interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
+	// 		     <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+	// 	interrupt-names = "int0", "int1";
+	// 	bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
+	// };
+
+	// main_mcan12: can@27c1000 {
+	// 	compatible = "bosch,m_can";
+	// 	reg = <0x00 0x027c1000 0x00 0x200>,
+	// 	      <0x00 0x027c8000 0x00 0x8000>;
+	// 	reg-names = "m_can", "message_ram";
+	// 	power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 170 1>, <&k3_clks 170 0>;
+	// 	clock-names = "cclk", "hclk";
+	// 	interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
+	// 		     <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
+	// 	interrupt-names = "int0", "int1";
+	// 	bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
+	// };
+
+	// main_mcan13: can@27d1000 {
+	// 	compatible = "bosch,m_can";
+	// 	reg = <0x00 0x027d1000 0x00 0x200>,
+	// 	      <0x00 0x027d8000 0x00 0x8000>;
+	// 	reg-names = "m_can", "message_ram";
+	// 	power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 171 1>, <&k3_clks 171 0>;
+	// 	clock-names = "cclk", "hclk";
+	// 	interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
+	// 		     <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
+	// 	interrupt-names = "int0", "int1";
+	// 	bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
+	// };
 
 };
diff --git a/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
index f0fba2bb1..997a25ee0 100644
--- a/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
+++ b/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
@@ -70,108 +70,108 @@
 		#size-cells = <1>;
 	};
 
-	wkup_uart0: serial@42300000 {
-		compatible = "ti,j721e-uart", "ti,am654-uart";
-		reg = <0x00 0x42300000 0x00 0x100>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <48000000>;
-		current-speed = <115200>;
-		power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 287 0>;
-		clock-names = "fclk";
-	};
-
-	mcu_uart0: serial@40a00000 {
-		compatible = "ti,j721e-uart", "ti,am654-uart";
-		reg = <0x00 0x40a00000 0x00 0x100>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <96000000>;
-		current-speed = <115200>;
-		power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 149 0>;
-		clock-names = "fclk";
-	};
-
-	wkup_gpio_intr: interrupt-controller2 {
-		compatible = "ti,sci-intr";
-		ti,intr-trigger-type = <1>;
-		interrupt-controller;
-		interrupt-parent = <&gic500>;
-		#interrupt-cells = <1>;
-		ti,sci = <&dmsc>;
-		ti,sci-dev-id = <137>;
-		ti,interrupt-ranges = <16 960 16>;
-		ti,sci-rm-range-girq = <0x5>;
-	};
-
-	wkup_gpio0: gpio@42110000 {
-		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
-		reg = <0x0 0x42110000 0x0 0x100>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		interrupt-parent = <&wkup_gpio_intr>;
-		interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		ti,ngpio = <84>;
-		ti,davinci-gpio-unbanked = <0>;
-		power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 113 0>;
-		clock-names = "gpio";
-	};
-
-	wkup_gpio1: gpio@42100000 {
-		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
-		reg = <0x0 0x42100000 0x0 0x100>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		interrupt-parent = <&wkup_gpio_intr>;
-		interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		ti,ngpio = <84>;
-		ti,davinci-gpio-unbanked = <0>;
-		power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 114 0>;
-		clock-names = "gpio";
-	};
-
-	mcu_i2c0: i2c@40b00000 {
-		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
-		reg = <0x0 0x40b00000 0x0 0x100>;
-		interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clock-names = "fck";
-		clocks = <&k3_clks 194 0>;
-		power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
-	};
-
-	mcu_i2c1: i2c@40b10000 {
-		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
-		reg = <0x0 0x40b10000 0x0 0x100>;
-		interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clock-names = "fck";
-		clocks = <&k3_clks 195 0>;
-		power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
-	};
-
-	wkup_i2c0: i2c@42120000 {
-		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
-		reg = <0x0 0x42120000 0x0 0x100>;
-		interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clock-names = "fck";
-		clocks = <&k3_clks 197 0>;
-		power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
-	};
+	// wkup_uart0: serial@42300000 {
+	// 	compatible = "ti,j721e-uart", "ti,am654-uart";
+	// 	reg = <0x00 0x42300000 0x00 0x100>;
+	// 	reg-shift = <2>;
+	// 	reg-io-width = <4>;
+	// 	interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
+	// 	clock-frequency = <48000000>;
+	// 	current-speed = <115200>;
+	// 	power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 287 0>;
+	// 	clock-names = "fclk";
+	// };
+
+	// mcu_uart0: serial@40a00000 {
+	// 	compatible = "ti,j721e-uart", "ti,am654-uart";
+	// 	reg = <0x00 0x40a00000 0x00 0x100>;
+	// 	reg-shift = <2>;
+	// 	reg-io-width = <4>;
+	// 	interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
+	// 	clock-frequency = <96000000>;
+	// 	current-speed = <115200>;
+	// 	power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 149 0>;
+	// 	clock-names = "fclk";
+	// };
+
+	// wkup_gpio_intr: interrupt-controller2 {
+	// 	compatible = "ti,sci-intr";
+	// 	ti,intr-trigger-type = <1>;
+	// 	interrupt-controller;
+	// 	interrupt-parent = <&gic500>;
+	// 	#interrupt-cells = <1>;
+	// 	ti,sci = <&dmsc>;
+	// 	ti,sci-dev-id = <137>;
+	// 	ti,interrupt-ranges = <16 960 16>;
+	// 	ti,sci-rm-range-girq = <0x5>;
+	// };
+
+	// wkup_gpio0: gpio@42110000 {
+	// 	compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+	// 	reg = <0x0 0x42110000 0x0 0x100>;
+	// 	gpio-controller;
+	// 	#gpio-cells = <2>;
+	// 	interrupt-parent = <&wkup_gpio_intr>;
+	// 	interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
+	// 	interrupt-controller;
+	// 	#interrupt-cells = <2>;
+	// 	ti,ngpio = <84>;
+	// 	ti,davinci-gpio-unbanked = <0>;
+	// 	power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 113 0>;
+	// 	clock-names = "gpio";
+	// };
+
+	// wkup_gpio1: gpio@42100000 {
+	// 	compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+	// 	reg = <0x0 0x42100000 0x0 0x100>;
+	// 	gpio-controller;
+	// 	#gpio-cells = <2>;
+	// 	interrupt-parent = <&wkup_gpio_intr>;
+	// 	interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
+	// 	interrupt-controller;
+	// 	#interrupt-cells = <2>;
+	// 	ti,ngpio = <84>;
+	// 	ti,davinci-gpio-unbanked = <0>;
+	// 	power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 114 0>;
+	// 	clock-names = "gpio";
+	// };
+
+	// mcu_i2c0: i2c@40b00000 {
+	// 	compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+	// 	reg = <0x0 0x40b00000 0x0 0x100>;
+	// 	interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
+	// 	#address-cells = <1>;
+	// 	#size-cells = <0>;
+	// 	clock-names = "fck";
+	// 	clocks = <&k3_clks 194 0>;
+	// 	power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
+	// };
+
+	// mcu_i2c1: i2c@40b10000 {
+	// 	compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+	// 	reg = <0x0 0x40b10000 0x0 0x100>;
+	// 	interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
+	// 	#address-cells = <1>;
+	// 	#size-cells = <0>;
+	// 	clock-names = "fck";
+	// 	clocks = <&k3_clks 195 0>;
+	// 	power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
+	// };
+
+	// wkup_i2c0: i2c@42120000 {
+	// 	compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+	// 	reg = <0x0 0x42120000 0x0 0x100>;
+	// 	interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
+	// 	#address-cells = <1>;
+	// 	#size-cells = <0>;
+	// 	clock-names = "fck";
+	// 	clocks = <&k3_clks 197 0>;
+	// 	power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
+	// };
 
 	fss: fss@47000000 {
 		compatible = "simple-bus";
@@ -197,52 +197,52 @@
 			#size-cells = <0>;
 		};
 
-		ospi1: spi@47050000 {
-			compatible = "ti,am654-ospi";
-			reg = <0x0 0x47050000 0x0 0x100>,
-				<0x7 0x00000000 0x1 0x00000000>;
-			interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
-			cdns,fifo-depth = <256>;
-			cdns,fifo-width = <4>;
-			cdns,trigger-address = <0x0>;
-			clocks = <&k3_clks 104 0>;
-			power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-	};
-
-	tscadc0: tscadc@40200000 {
-		compatible = "ti,am3359-tscadc";
-		reg = <0x0 0x40200000 0x0 0x1000>;
-		interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
-		power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 0 1>;
-		assigned-clocks = <&k3_clks 0 3>;
-		assigned-clock-rates = <60000000>;
-		clock-names = "adc_tsc_fck";
-
-		adc {
-			#io-channel-cells = <1>;
-			compatible = "ti,am3359-adc";
-		};
+		// ospi1: spi@47050000 {
+		// 	compatible = "ti,am654-ospi";
+		// 	reg = <0x0 0x47050000 0x0 0x100>,
+		// 		<0x7 0x00000000 0x1 0x00000000>;
+		// 	interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
+		// 	cdns,fifo-depth = <256>;
+		// 	cdns,fifo-width = <4>;
+		// 	cdns,trigger-address = <0x0>;
+		// 	clocks = <&k3_clks 104 0>;
+		// 	power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
+		// 	#address-cells = <1>;
+		// 	#size-cells = <0>;
+		// };
 	};
 
-	tscadc1: tscadc@40210000 {
-		compatible = "ti,am3359-tscadc";
-		reg = <0x0 0x40210000 0x0 0x1000>;
-		interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>;
-		power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 1 1>;
-		assigned-clocks = <&k3_clks 1 3>;
-		assigned-clock-rates = <60000000>;
-		clock-names = "adc_tsc_fck";
-
-		adc {
-			#io-channel-cells = <1>;
-			compatible = "ti,am3359-adc";
-		};
-	};
+	// tscadc0: tscadc@40200000 {
+	// 	compatible = "ti,am3359-tscadc";
+	// 	reg = <0x0 0x40200000 0x0 0x1000>;
+	// 	interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
+	// 	power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 0 1>;
+	// 	assigned-clocks = <&k3_clks 0 3>;
+	// 	assigned-clock-rates = <60000000>;
+	// 	clock-names = "adc_tsc_fck";
+
+	// 	adc {
+	// 		#io-channel-cells = <1>;
+	// 		compatible = "ti,am3359-adc";
+	// 	};
+	// };
+
+	// tscadc1: tscadc@40210000 {
+	// 	compatible = "ti,am3359-tscadc";
+	// 	reg = <0x0 0x40210000 0x0 0x1000>;
+	// 	interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>;
+	// 	power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 1 1>;
+	// 	assigned-clocks = <&k3_clks 1 3>;
+	// 	assigned-clock-rates = <60000000>;
+	// 	clock-names = "adc_tsc_fck";
+
+	// 	adc {
+	// 		#io-channel-cells = <1>;
+	// 		compatible = "ti,am3359-adc";
+	// 	};
+	// };
 
 	cbass_mcu_navss: navss@28380000 {
 		compatible = "simple-mfd";
@@ -289,65 +289,65 @@
 		};
 	};
 
-	mcu_cpsw: ethernet@46000000 {
-		compatible = "ti,j721e-cpsw-nuss";
-		#address-cells = <2>;
-		#size-cells = <2>;
-		reg = <0x0 0x46000000 0x0 0x200000>;
-		reg-names = "cpsw_nuss";
-		ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
-		dma-coherent;
-		clocks = <&k3_clks 18 22>;
-		clock-names = "fck";
-		power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
-
-		dmas = <&mcu_udmap 0xf000>,
-		       <&mcu_udmap 0xf001>,
-		       <&mcu_udmap 0xf002>,
-		       <&mcu_udmap 0xf003>,
-		       <&mcu_udmap 0xf004>,
-		       <&mcu_udmap 0xf005>,
-		       <&mcu_udmap 0xf006>,
-		       <&mcu_udmap 0xf007>,
-		       <&mcu_udmap 0x7000>;
-		dma-names = "tx0", "tx1", "tx2", "tx3",
-			    "tx4", "tx5", "tx6", "tx7",
-			    "rx";
-
-		ethernet-ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			cpsw_port1: port@1 {
-				reg = <1>;
-				ti,mac-only;
-				label = "port1";
-				ti,syscon-efuse = <&mcu_conf 0x200>;
-				phys = <&phy_gmii_sel 1>;
-			};
-		};
-
-		davinci_mdio: mdio@f00 {
-			compatible = "ti,cpsw-mdio","ti,davinci_mdio";
-			reg = <0x0 0xf00 0x0 0x100>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			clocks = <&k3_clks 18 22>;
-			clock-names = "fck";
-			bus_freq = <1000000>;
-		};
-
-		cpts@3d000 {
-			compatible = "ti,am65-cpts";
-			reg = <0x0 0x3d000 0x0 0x400>;
-			clocks = <&k3_clks 18 2>;
-			clock-names = "cpts";
-			interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "cpts";
-			ti,cpts-ext-ts-inputs = <4>;
-			ti,cpts-periodic-outputs = <2>;
-		};
-	};
+	// mcu_cpsw: ethernet@46000000 {
+	// 	compatible = "ti,j721e-cpsw-nuss";
+	// 	#address-cells = <2>;
+	// 	#size-cells = <2>;
+	// 	reg = <0x0 0x46000000 0x0 0x200000>;
+	// 	reg-names = "cpsw_nuss";
+	// 	ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
+	// 	dma-coherent;
+	// 	clocks = <&k3_clks 18 22>;
+	// 	clock-names = "fck";
+	// 	power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
+
+	// 	dmas = <&mcu_udmap 0xf000>,
+	// 	       <&mcu_udmap 0xf001>,
+	// 	       <&mcu_udmap 0xf002>,
+	// 	       <&mcu_udmap 0xf003>,
+	// 	       <&mcu_udmap 0xf004>,
+	// 	       <&mcu_udmap 0xf005>,
+	// 	       <&mcu_udmap 0xf006>,
+	// 	       <&mcu_udmap 0xf007>,
+	// 	       <&mcu_udmap 0x7000>;
+	// 	dma-names = "tx0", "tx1", "tx2", "tx3",
+	// 		    "tx4", "tx5", "tx6", "tx7",
+	// 		    "rx";
+
+	// 	ethernet-ports {
+	// 		#address-cells = <1>;
+	// 		#size-cells = <0>;
+
+	// 		cpsw_port1: port@1 {
+	// 			reg = <1>;
+	// 			ti,mac-only;
+	// 			label = "port1";
+	// 			ti,syscon-efuse = <&mcu_conf 0x200>;
+	// 			phys = <&phy_gmii_sel 1>;
+	// 		};
+	// 	};
+
+	// 	davinci_mdio: mdio@f00 {
+	// 		compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+	// 		reg = <0x0 0xf00 0x0 0x100>;
+	// 		#address-cells = <1>;
+	// 		#size-cells = <0>;
+	// 		clocks = <&k3_clks 18 22>;
+	// 		clock-names = "fck";
+	// 		bus_freq = <1000000>;
+	// 	};
+
+	// 	cpts@3d000 {
+	// 		compatible = "ti,am65-cpts";
+	// 		reg = <0x0 0x3d000 0x0 0x400>;
+	// 		clocks = <&k3_clks 18 2>;
+	// 		clock-names = "cpts";
+	// 		interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
+	// 		interrupt-names = "cpts";
+	// 		ti,cpts-ext-ts-inputs = <4>;
+	// 		ti,cpts-periodic-outputs = <2>;
+	// 	};
+	// };
 
 	mcu_r5fss0: r5fss@41000000 {
 		compatible = "ti,j721e-r5fss";
@@ -389,31 +389,43 @@
 		};
 	};
 
-	mcu_mcan0: can@40528000 {
-		compatible = "bosch,m_can";
-		reg = <0x00 0x40528000 0x00 0x200>,
-		      <0x00 0x40500000 0x00 0x8000>;
-		reg-names = "m_can", "message_ram";
-		power-domains = <&k3_pds 172 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 172 1>, <&k3_clks 172 0>;
-		clock-names = "cclk", "hclk";
-		interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "int0", "int1";
-		bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
-	};
-
-	mcu_mcan1: can@40568000 {
-		compatible = "bosch,m_can";
-		reg = <0x00 0x40568000 0x00 0x200>,
-		      <0x00 0x40540000 0x00 0x8000>;
-		reg-names = "m_can", "message_ram";
-		power-domains = <&k3_pds 173 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 173 1>, <&k3_clks 173 0>;
-		clock-names = "cclk", "hclk";
-		interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "int0", "int1";
-		bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
-	};
+	// mcu_mcan0: can@40528000 {
+	// 	compatible = "bosch,m_can";
+	// 	reg = <0x00 0x40528000 0x00 0x200>,
+	// 	      <0x00 0x40500000 0x00 0x8000>;
+	// 	reg-names = "m_can", "message_ram";
+	// 	power-domains = <&k3_pds 172 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 172 1>, <&k3_clks 172 0>;
+	// 	clock-names = "cclk", "hclk";
+	// 	interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>,
+	// 		     <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
+	// 	interrupt-names = "int0", "int1";
+	// 	bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
+	// };
+
+	// mcu_mcan1: can@40568000 {
+	// 	compatible = "bosch,m_can";
+	// 	reg = <0x00 0x40568000 0x00 0x200>,
+	// 	      <0x00 0x40540000 0x00 0x8000>;
+	// 	reg-names = "m_can", "message_ram";
+	// 	power-domains = <&k3_pds 173 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 173 1>, <&k3_clks 173 0>;
+	// 	clock-names = "cclk", "hclk";
+	// 	interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>,
+	// 		     <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
+	// 	interrupt-names = "int0", "int1";
+	// 	bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
+	// };
+		wkup_vtm0: wkup_vtm0@42040000 {
+                compatible = "ti,j721e-vtm";
+                reg = <0x0 0x42040000 0x0 0x350>,
+                        <0x0 0x42050000 0x0 0x350>,
+                        <0x0 0x43000300 0x0 0x10>;
+                power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
+                #thermal-sensor-cells = <1>;
+        };
+		
+        thermal_zones: thermal-zones {
+                #include "k3-j721e-thermal.dtsi"
+        };
 };
diff --git a/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e-proc-board-tps65917.dts b/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e-proc-board-tps65917.dts
index 020b6e44e..c51d3a7ac 100644
--- a/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e-proc-board-tps65917.dts
+++ b/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e-proc-board-tps65917.dts
@@ -7,60 +7,60 @@
 
 #include "k3-j721e-common-proc-board.dts"
 
-&wkup_i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&wkup_i2c0_pins_default>;
-	clock-frequency = <400000>;
+// &wkup_i2c0 {
+// 	pinctrl-names = "default";
+// 	pinctrl-0 = <&wkup_i2c0_pins_default>;
+// 	clock-frequency = <400000>;
 
-	tps65917: tps65917@58 {
-		reg = <0x58>;
-		compatible = "ti,tps65917";
+// 	tps65917: tps65917@58 {
+// 		reg = <0x58>;
+// 		compatible = "ti,tps65917";
 
-		tps65917_pmic {
-			compatible = "ti,tps65917-pmic";
+// 		tps65917_pmic {
+// 			compatible = "ti,tps65917-pmic";
 
-			ldo1-in-supply = <&vsys_3v3>;
+// 			ldo1-in-supply = <&vsys_3v3>;
 
-			tps65917_regulators: regulators {
-				ldo1_reg: ldo1 {
-					/* LDO1_OUT --> VDD_SD_DV_REG  */
-					regulator-name = "ldo1";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <3300000>;
-					regulator-allow-bypass;
-				};
+// 			tps65917_regulators: regulators {
+// 				ldo1_reg: ldo1 {
+// 					/* LDO1_OUT --> VDD_SD_DV_REG  */
+// 					regulator-name = "ldo1";
+// 					regulator-min-microvolt = <1800000>;
+// 					regulator-max-microvolt = <3300000>;
+// 					regulator-allow-bypass;
+// 				};
 
-				ldo2_reg: ldo2 {
-					/* LDO2_OUT --> VDA_USB_3V3_REG  */
-					regulator-name = "ldo2";
-					regulator-min-microvolt = <3300000>;
-					regulator-max-microvolt = <3300000>;
-					regulator-allow-bypass;
-					regulator-always-on;
-					regulator-boot-on;
-				};
-			};
-		};
-	};
-};
+// 				ldo2_reg: ldo2 {
+// 					/* LDO2_OUT --> VDA_USB_3V3_REG  */
+// 					regulator-name = "ldo2";
+// 					regulator-min-microvolt = <3300000>;
+// 					regulator-max-microvolt = <3300000>;
+// 					regulator-allow-bypass;
+// 					regulator-always-on;
+// 					regulator-boot-on;
+// 				};
+// 			};
+// 		};
+// 	};
+// };
 
-&mcasp10_pins_default {
-	pinctrl-single,pins = <
-		J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */
-		J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */
-		J721E_IOPAD(0x160, PIN_INPUT_PULLDOWN, 12) /* (V28) RGMII5_TD3.MCASP10_AXR0 */
-		J721E_IOPAD(0x164, PIN_INPUT_PULLDOWN, 12) /* (V29) RGMII5_TD2.MCASP10_AXR1 */
-		J721E_IOPAD(0x170, PIN_INPUT_PULLDOWN, 12) /* (U29) RGMII5_TXC.MCASP10_AXR2 */
-		J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 12) /* (U25) RGMII5_RXC.MCASP10_AXR3 */
-		J721E_IOPAD(0x198, PIN_OUTPUT_PULLDOWN, 12) /* (V25) RGMII6_TD1.MCASP10_AXR4 */
-		J721E_IOPAD(0x19c, PIN_OUTPUT_PULLDOWN, 12) /* (W27) RGMII6_TD0.MCASP10_AXR5 */
-		J721E_IOPAD(0x1a0, PIN_OUTPUT_PULLDOWN, 12) /* (W29) RGMII6_TXC.MCASP10_AXR6 */
-	>;
-};
+// &mcasp10_pins_default {
+// 	pinctrl-single,pins = <
+// 		J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */
+// 		J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */
+// 		J721E_IOPAD(0x160, PIN_INPUT_PULLDOWN, 12) /* (V28) RGMII5_TD3.MCASP10_AXR0 */
+// 		J721E_IOPAD(0x164, PIN_INPUT_PULLDOWN, 12) /* (V29) RGMII5_TD2.MCASP10_AXR1 */
+// 		J721E_IOPAD(0x170, PIN_INPUT_PULLDOWN, 12) /* (U29) RGMII5_TXC.MCASP10_AXR2 */
+// 		J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 12) /* (U25) RGMII5_RXC.MCASP10_AXR3 */
+// 		J721E_IOPAD(0x198, PIN_OUTPUT_PULLDOWN, 12) /* (V25) RGMII6_TD1.MCASP10_AXR4 */
+// 		J721E_IOPAD(0x19c, PIN_OUTPUT_PULLDOWN, 12) /* (W27) RGMII6_TD0.MCASP10_AXR5 */
+// 		J721E_IOPAD(0x1a0, PIN_OUTPUT_PULLDOWN, 12) /* (W29) RGMII6_TXC.MCASP10_AXR6 */
+// 	>;
+// };
 
-&mcasp10 {
-	serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
-		2 2 2 1
-		1 1 1 0
-	>;
-};
+// &mcasp10 {
+// 	serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
+// 		2 2 2 1
+// 		1 1 1 0
+// 	>;
+// };
diff --git a/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
index 90bcc6be3..b94a2e67f 100644
--- a/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
+++ b/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
@@ -176,12 +176,12 @@
 		reg = <0x0>;
 		spi-tx-bus-width = <8>;
 		spi-rx-bus-width = <8>;
-		spi-max-frequency = <25000000>;
+		spi-max-frequency = <40000000>;
 		cdns,tshsl-ns = <60>;
 		cdns,tsd2d-ns = <60>;
 		cdns,tchsh-ns = <60>;
 		cdns,tslch-ns = <60>;
-		cdns,read-delay = <0>;
+		cdns,read-delay = <2>;
 		cdns,phy-mode;
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -236,3 +236,97 @@
 	memory-region = <&c71_0_dma_memory_region>,
 			<&c71_0_memory_region>;
 };
+
+&rtos_ipc_memory_region {
+	reg = <0x00 0xaa000000 0x00 0x02000000>;
+};
+
+&reserved_memory {
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	vision_apps_main_r5fss0_core0_dma_memory_region: vision_apps-r5f-dma-memory@a1000000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xa1000000 0x00 0x00100000>;
+		no-map;
+	};
+	vision_apps_main_r5fss0_core0_memory_region: vision_apps-r5f-memory@a1100000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xa1100000 0x00 0x01f00000>;
+		no-map;
+	};
+	vision_apps_main_r5fss0_core1_memory_region: vision_apps-r5f-memory@a3100000 {
+	    compatible = "shared-dma-pool";
+	    reg = <0x00 0xa3100000 0x00 0x01f00000>;
+	    no-map;
+	};
+	vision_apps_main_r5fss1_core0_dma_memory_region: vision_apps-r5f-dma-memory@a5000000 {
+	    compatible = "shared-dma-pool";
+	    reg = <0x00 0xa5000000 0x00 0x100000>;
+	    no-map;
+	};
+	vision_apps_main_r5fss1_core0_memory_region: vision_apps-r5f-memory@a5100000 {
+	    compatible = "shared-dma-pool";
+	    reg = <0x00 0xa5100000 0x00 0x00700000>;
+	    no-map;
+	};
+	vision_apps_main_r5fss1_core1_dma_memory_region: vision_apps-r5f-dma-memory@a5800000 {
+	    compatible = "shared-dma-pool";
+	    reg = <0x00 0xa5800000 0x00 0x100000>;
+	    no-map;
+	};
+	vision_apps_main_r5fss1_core1_memory_region: vision_apps-r5f-memory@a5900000 {
+	    compatible = "shared-dma-pool";
+	    reg = <0x00 0xa5900000 0x00 0x00700000>;
+	    no-map;
+	};
+	vision_apps_memory_region: vision_apps-dma-memory@ac000000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xac000000 0x00 0x02000000>;
+		no-map;
+	};
+	vision_apps_shared_region: vision_apps_shared-memories {
+		compatible = "dma-heap-carveout";
+		reg = <0x00 0xae000000 0x00 0x20000000>;
+	};
+	vision_apps_core_heaps: vision_apps-core-heap-memory@ce000000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xce000000 0x00 0x2d000000>;
+		no-map;
+	};
+	vision_apps_mcu_r5fss0_core1_dma_memory_region: vision_apps-r5f-dma-memory@fb000000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xfb000000 0x00 0x00100000>;
+		no-map;
+	};
+	vision_apps_mcu_r5fss0_core1_memory_region: vision_apps-r5f-memory@fb100000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xfb100000 0x00 0x00f00000>;
+		no-map;
+	};
+};
+
+&mcu_r5fss0_core1 {
+	memory-region = <&vision_apps_mcu_r5fss0_core1_dma_memory_region>,
+			<&vision_apps_mcu_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss0_core0 {
+	memory-region = <&vision_apps_main_r5fss0_core0_dma_memory_region>,
+			<&vision_apps_main_r5fss0_core0_memory_region>;
+};
+
+&main_r5fss0_core1 {
+	memory-region = <&main_r5fss0_core1_dma_memory_region>,
+			<&vision_apps_main_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss1_core0 {
+	memory-region = <&vision_apps_main_r5fss1_core0_dma_memory_region>,
+			<&vision_apps_main_r5fss1_core0_memory_region>;
+};
+
+&main_r5fss1_core1 {
+	memory-region = <&vision_apps_main_r5fss1_core1_dma_memory_region>,
+			<&vision_apps_main_r5fss1_core1_memory_region>;
+};
diff --git a/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi b/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi
new file mode 100644
index 000000000..e922042f3
--- /dev/null
+++ b/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/thermal/thermal.h>
+
+wkup_thermal: wkup_thermal {
+	polling-delay-passive = <250>; /* milliseconds */
+	polling-delay = <500>; /* milliseconds */
+	thermal-sensors = <&wkup_vtm0 0>;
+
+	trips {
+		wkup_crit: wkup_crit {
+			temperature = <125000>; /* milliCelsius */
+			hysteresis = <2000>; /* milliCelsius */
+			type = "critical";
+		};
+	};
+};
+
+mpu_thermal: mpu_thermal {
+	polling-delay-passive = <250>; /* milliseconds */
+	polling-delay = <500>; /* milliseconds */
+	thermal-sensors = <&wkup_vtm0 1>;
+
+	trips {
+		mpu_crit: mpu_crit {
+			temperature = <125000>; /* milliCelsius */
+			hysteresis = <2000>; /* milliCelsius */
+			type = "critical";
+		};
+	};
+};
+
+c7x_thermal: c7x_thermal {
+	polling-delay-passive = <250>; /* milliseconds */
+	polling-delay = <500>; /* milliseconds */
+	thermal-sensors = <&wkup_vtm0 2>;
+
+	trips {
+		c7x_crit: c7x_crit {
+			temperature = <125000>; /* milliCelsius */
+			hysteresis = <2000>; /* milliCelsius */
+			type = "critical";
+		};
+	};
+};
+
+gpu_thermal: gpu_thermal {
+	polling-delay-passive = <250>; /* milliseconds */
+	polling-delay = <500>; /* milliseconds */
+	thermal-sensors = <&wkup_vtm0 3>;
+
+	trips {
+		gpu_crit: gpu_crit {
+			temperature = <125000>; /* milliCelsius */
+			hysteresis = <2000>; /* milliCelsius */
+			type = "critical";
+		};
+	};
+};
+
+r5f_thermal: r5f_thermal {
+	polling-delay-passive = <250>; /* milliseconds */
+	polling-delay = <500>; /* milliseconds */
+	thermal-sensors = <&wkup_vtm0 4>;
+
+	trips {
+		r5f_crit: r5f_crit {
+			temperature = <125000>; /* milliCelsius */
+			hysteresis = <2000>; /* milliCelsius */
+			type = "critical";
+		};
+	};
+};
diff --git a/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e-vision-apps.dtso b/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e-vision-apps.dtso
index f2719997f..9f9cb8666 100644
--- a/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e-vision-apps.dtso
+++ b/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e-vision-apps.dtso
@@ -23,152 +23,152 @@
 	};
 };
 
-&mcu_r5fss0_core1_dma_memory_region {
-	status = "disabled";
-};
-
-&mcu_r5fss0_core1_memory_region {
-	status = "disabled";
-};
-
-&main_r5fss0_core0_dma_memory_region {
-	status = "disabled";
-};
-
-&main_r5fss0_core0_memory_region {
-	status = "disabled";
-};
-
-&main_r5fss0_core1_memory_region {
-	status = "disabled";
-};
-
-&main_r5fss1_core0_dma_memory_region {
-	status = "disabled";
-};
-
-&main_r5fss1_core0_memory_region {
-	status = "disabled";
-};
-
-&main_r5fss1_core1_dma_memory_region {
-	status = "disabled";
-};
-
-&main_r5fss1_core1_memory_region {
-	status = "disabled";
-};
-
-&rtos_ipc_memory_region {
-	reg = <0x00 0xaa000000 0x00 0x02000000>;
-};
-
-&reserved_memory {
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	vision_apps_main_r5fss0_core0_dma_memory_region: vision_apps-r5f-dma-memory@a1000000 {
-		compatible = "shared-dma-pool";
-		reg = <0x00 0xa1000000 0x00 0x00100000>;
-		no-map;
-	};
-	vision_apps_main_r5fss0_core0_memory_region: vision_apps-r5f-memory@a1100000 {
-		compatible = "shared-dma-pool";
-		reg = <0x00 0xa1100000 0x00 0x01f00000>;
-		no-map;
-	};
-	vision_apps_main_r5fss0_core1_memory_region: vision_apps-r5f-memory@a3100000 {
-	    compatible = "shared-dma-pool";
-	    reg = <0x00 0xa3100000 0x00 0x01f00000>;
-	    no-map;
-	};
-	vision_apps_main_r5fss1_core0_dma_memory_region: vision_apps-r5f-dma-memory@a5000000 {
-	    compatible = "shared-dma-pool";
-	    reg = <0x00 0xa5000000 0x00 0x100000>;
-	    no-map;
-	};
-	vision_apps_main_r5fss1_core0_memory_region: vision_apps-r5f-memory@a5100000 {
-	    compatible = "shared-dma-pool";
-	    reg = <0x00 0xa5100000 0x00 0x00700000>;
-	    no-map;
-	};
-	vision_apps_main_r5fss1_core1_dma_memory_region: vision_apps-r5f-dma-memory@a5800000 {
-	    compatible = "shared-dma-pool";
-	    reg = <0x00 0xa5800000 0x00 0x100000>;
-	    no-map;
-	};
-	vision_apps_main_r5fss1_core1_memory_region: vision_apps-r5f-memory@a5900000 {
-	    compatible = "shared-dma-pool";
-	    reg = <0x00 0xa5900000 0x00 0x00700000>;
-	    no-map;
-	};
-	vision_apps_memory_region: vision_apps-dma-memory@ac000000 {
-		compatible = "shared-dma-pool";
-		reg = <0x00 0xac000000 0x00 0x02000000>;
-		no-map;
-	};
-	vision_apps_shared_region: vision_apps_shared-memories {
-		compatible = "dma-heap-carveout";
-		reg = <0x00 0xae000000 0x00 0x20000000>;
-	};
-	vision_apps_core_heaps: vision_apps-core-heap-memory@ce000000 {
-		compatible = "shared-dma-pool";
-		reg = <0x00 0xce000000 0x00 0x2d000000>;
-		no-map;
-	};
-	vision_apps_mcu_r5fss0_core1_dma_memory_region: vision_apps-r5f-dma-memory@fb000000 {
-		compatible = "shared-dma-pool";
-		reg = <0x00 0xfb000000 0x00 0x00100000>;
-		no-map;
-	};
-	vision_apps_mcu_r5fss0_core1_memory_region: vision_apps-r5f-memory@fb100000 {
-		compatible = "shared-dma-pool";
-		reg = <0x00 0xfb100000 0x00 0x00f00000>;
-		no-map;
-	};
-};
-
-&mcu_r5fss0_core1 {
-	memory-region = <&vision_apps_mcu_r5fss0_core1_dma_memory_region>,
-			<&vision_apps_mcu_r5fss0_core1_memory_region>;
-};
-
-&main_r5fss0_core0 {
-	memory-region = <&vision_apps_main_r5fss0_core0_dma_memory_region>,
-			<&vision_apps_main_r5fss0_core0_memory_region>;
-};
-
-&main_r5fss0_core1 {
-	memory-region = <&main_r5fss0_core1_dma_memory_region>,
-			<&vision_apps_main_r5fss0_core1_memory_region>;
-};
-
-&main_r5fss1_core0 {
-	memory-region = <&vision_apps_main_r5fss1_core0_dma_memory_region>,
-			<&vision_apps_main_r5fss1_core0_memory_region>;
-};
-
-&main_r5fss1_core1 {
-	memory-region = <&vision_apps_main_r5fss1_core1_dma_memory_region>,
-			<&vision_apps_main_r5fss1_core1_memory_region>;
-};
-
-&main_i2c6 {
-	status = "disabled";
-};
-
-&serdes_wiz4 {
-	status = "disabled";
-};
-
-&mhdp {
-	status = "disabled";
-};
-
-&dss {
-	status = "disabled";
-};
-
-&main_i2c1 {
-	status = "disabled";
-};
+// &mcu_r5fss0_core1_dma_memory_region {
+// 	status = "disabled";
+// };
+
+// &mcu_r5fss0_core1_memory_region {
+// 	status = "disabled";
+// };
+
+// &main_r5fss0_core0_dma_memory_region {
+// 	status = "disabled";
+// };
+
+// &main_r5fss0_core0_memory_region {
+// 	status = "disabled";
+// };
+
+// &main_r5fss0_core1_memory_region {
+// 	status = "disabled";
+// };
+
+// &main_r5fss1_core0_dma_memory_region {
+// 	status = "disabled";
+// };
+
+// &main_r5fss1_core0_memory_region {
+// 	status = "disabled";
+// };
+
+// &main_r5fss1_core1_dma_memory_region {
+// 	status = "disabled";
+// };
+
+// &main_r5fss1_core1_memory_region {
+// 	status = "disabled";
+// };
+
+// &rtos_ipc_memory_region {
+// 	reg = <0x00 0xaa000000 0x00 0x02000000>;
+// };
+
+// &reserved_memory {
+// 	#address-cells = <2>;
+// 	#size-cells = <2>;
+
+// 	vision_apps_main_r5fss0_core0_dma_memory_region: vision_apps-r5f-dma-memory@a1000000 {
+// 		compatible = "shared-dma-pool";
+// 		reg = <0x00 0xa1000000 0x00 0x00100000>;
+// 		no-map;
+// 	};
+// 	vision_apps_main_r5fss0_core0_memory_region: vision_apps-r5f-memory@a1100000 {
+// 		compatible = "shared-dma-pool";
+// 		reg = <0x00 0xa1100000 0x00 0x01f00000>;
+// 		no-map;
+// 	};
+// 	vision_apps_main_r5fss0_core1_memory_region: vision_apps-r5f-memory@a3100000 {
+// 	    compatible = "shared-dma-pool";
+// 	    reg = <0x00 0xa3100000 0x00 0x01f00000>;
+// 	    no-map;
+// 	};
+// 	vision_apps_main_r5fss1_core0_dma_memory_region: vision_apps-r5f-dma-memory@a5000000 {
+// 	    compatible = "shared-dma-pool";
+// 	    reg = <0x00 0xa5000000 0x00 0x100000>;
+// 	    no-map;
+// 	};
+// 	vision_apps_main_r5fss1_core0_memory_region: vision_apps-r5f-memory@a5100000 {
+// 	    compatible = "shared-dma-pool";
+// 	    reg = <0x00 0xa5100000 0x00 0x00700000>;
+// 	    no-map;
+// 	};
+// 	vision_apps_main_r5fss1_core1_dma_memory_region: vision_apps-r5f-dma-memory@a5800000 {
+// 	    compatible = "shared-dma-pool";
+// 	    reg = <0x00 0xa5800000 0x00 0x100000>;
+// 	    no-map;
+// 	};
+// 	vision_apps_main_r5fss1_core1_memory_region: vision_apps-r5f-memory@a5900000 {
+// 	    compatible = "shared-dma-pool";
+// 	    reg = <0x00 0xa5900000 0x00 0x00700000>;
+// 	    no-map;
+// 	};
+// 	vision_apps_memory_region: vision_apps-dma-memory@ac000000 {
+// 		compatible = "shared-dma-pool";
+// 		reg = <0x00 0xac000000 0x00 0x02000000>;
+// 		no-map;
+// 	};
+// 	vision_apps_shared_region: vision_apps_shared-memories {
+// 		compatible = "dma-heap-carveout";
+// 		reg = <0x00 0xae000000 0x00 0x20000000>;
+// 	};
+// 	vision_apps_core_heaps: vision_apps-core-heap-memory@ce000000 {
+// 		compatible = "shared-dma-pool";
+// 		reg = <0x00 0xce000000 0x00 0x2d000000>;
+// 		no-map;
+// 	};
+// 	vision_apps_mcu_r5fss0_core1_dma_memory_region: vision_apps-r5f-dma-memory@fb000000 {
+// 		compatible = "shared-dma-pool";
+// 		reg = <0x00 0xfb000000 0x00 0x00100000>;
+// 		no-map;
+// 	};
+// 	vision_apps_mcu_r5fss0_core1_memory_region: vision_apps-r5f-memory@fb100000 {
+// 		compatible = "shared-dma-pool";
+// 		reg = <0x00 0xfb100000 0x00 0x00f00000>;
+// 		no-map;
+// 	};
+// };
+
+// &mcu_r5fss0_core1 {
+// 	memory-region = <&vision_apps_mcu_r5fss0_core1_dma_memory_region>,
+// 			<&vision_apps_mcu_r5fss0_core1_memory_region>;
+// };
+
+// &main_r5fss0_core0 {
+// 	memory-region = <&vision_apps_main_r5fss0_core0_dma_memory_region>,
+// 			<&vision_apps_main_r5fss0_core0_memory_region>;
+// };
+
+// &main_r5fss0_core1 {
+// 	memory-region = <&main_r5fss0_core1_dma_memory_region>,
+// 			<&vision_apps_main_r5fss0_core1_memory_region>;
+// };
+
+// &main_r5fss1_core0 {
+// 	memory-region = <&vision_apps_main_r5fss1_core0_dma_memory_region>,
+// 			<&vision_apps_main_r5fss1_core0_memory_region>;
+// };
+
+// &main_r5fss1_core1 {
+// 	memory-region = <&vision_apps_main_r5fss1_core1_dma_memory_region>,
+// 			<&vision_apps_main_r5fss1_core1_memory_region>;
+// };
+
+// &main_i2c6 {
+// 	status = "disabled";
+// };
+
+// &serdes_wiz4 {
+// 	status = "disabled";
+// };
+
+// &mhdp {
+// 	status = "disabled";
+// };
+
+// &dss {
+// 	status = "disabled";
+// };
+
+// &main_i2c1 {
+// 	status = "disabled";
+// };
diff --git a/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
index 8c19acc26..8bf16c480 100644
--- a/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
+++ b/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
@@ -18,19 +18,19 @@
 	#size-cells = <2>;
 
 	aliases {
-		serial0 = &wkup_uart0;
-		serial1 = &mcu_uart0;
+		// serial0 = &wkup_uart0;
+		// serial1 = &mcu_uart0;
 		serial2 = &main_uart0;
-		serial3 = &main_uart1;
-		serial4 = &main_uart2;
-		serial5 = &main_uart3;
-		serial6 = &main_uart4;
-		serial7 = &main_uart5;
-		serial8 = &main_uart6;
-		serial9 = &main_uart7;
-		serial10 = &main_uart8;
-		serial11 = &main_uart9;
-		ethernet0 = &cpsw_port1;
+		// serial3 = &main_uart1;
+		// serial4 = &main_uart2;
+		// serial5 = &main_uart3;
+		// serial6 = &main_uart4;
+		// serial7 = &main_uart5;
+		// serial8 = &main_uart6;
+		// serial9 = &main_uart7;
+		// serial10 = &main_uart8;
+		// serial11 = &main_uart9;
+		// ethernet0 = &cpsw_port1;
 		rproc0 = &mcu_r5fss0_core0;
 		rproc1 = &mcu_r5fss0_core1;
 		rproc2 = &main_r5fss0_core0;	
diff --git a/board-support/u-boot-2020.01+gitAUTOINC+3c9ebdb87d-g3c9ebdb87d/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/board-support/u-boot-2020.01+gitAUTOINC+3c9ebdb87d-g3c9ebdb87d/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
index d15689a62..64c9391bc 100644
--- a/board-support/u-boot-2020.01+gitAUTOINC+3c9ebdb87d-g3c9ebdb87d/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
+++ b/board-support/u-boot-2020.01+gitAUTOINC+3c9ebdb87d-g3c9ebdb87d/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
@@ -12,7 +12,7 @@
 	};
 
 	aliases {
-		ethernet0 = &cpsw_port1;
+		// ethernet0 = &cpsw_port1;
 	};
 };
 
@@ -68,32 +68,32 @@
 	u-boot,dm-spl;
 };
 
-&wkup_pmx0 {
-	u-boot,dm-spl;
-	mcu_cpsw_pins_default: mcu_cpsw_pins_default {
-		pinctrl-single,pins = <
-			J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
-			J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
-			J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
-			J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
-			J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
-			J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
-			J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
-			J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
-			J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
-			J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
-			J721E_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
-			J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
-		>;
-	};
-
-	mcu_mdio_pins_default: mcu_mdio1_pins_default {
-		pinctrl-single,pins = <
-			J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
-			J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
-		>;
-	};
-};
+// &wkup_pmx0 {
+// 	u-boot,dm-spl;
+// 	mcu_cpsw_pins_default: mcu_cpsw_pins_default {
+// 		pinctrl-single,pins = <
+// 			J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
+// 			J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
+// 			J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
+// 			J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
+// 			J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
+// 			J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
+// 			J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
+// 			J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
+// 			J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
+// 			J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
+// 			J721E_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
+// 			J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
+// 		>;
+// 	};
+
+// 	mcu_mdio_pins_default: mcu_mdio1_pins_default {
+// 		pinctrl-single,pins = <
+// 			J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
+// 			J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
+// 		>;
+// 	};
+// };
 
 &main_pmx0 {
 	u-boot,dm-spl;
@@ -110,11 +110,11 @@
 	u-boot,dm-spl;
 };
 
-&main_uart1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_uart1_pins_default>;
-	status = "okay";
-};
+// &main_uart1 {
+// 	pinctrl-names = "default";
+// 	pinctrl-0 = <&main_uart1_pins_default>;
+// 	status = "okay";
+// };
 
 &mcu_uart0 {
 	u-boot,dm-spl;
@@ -128,74 +128,74 @@
 	u-boot,dm-spl;
 };
 
-&main_usbss0_pins_default {
-	u-boot,dm-spl;
-};
-
-&usbss0 {
-	u-boot,dm-spl;
-	ti,usb2-only;
-};
-
-&usb0 {
-	dr_mode = "peripheral";
-	u-boot,dm-spl;
-};
-
-&mcu_cpsw {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
-};
-
-&davinci_mdio {
-	phy0: ethernet-phy@0 {
-		reg = <0>;
-		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
-		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
-	};
-};
-
-&cpsw_port1 {
-	phy-mode = "rgmii-rxid";
-	phy-handle = <&phy0>;
-};
-
-&mcu_cpsw {
-	reg = <0x0 0x46000000 0x0 0x200000>,
-	      <0x0 0x40f00200 0x0 0x2>;
-	reg-names = "cpsw_nuss", "mac_efuse";
-	/delete-property/ ranges;
-
-	cpsw-phy-sel@40f04040 {
-		compatible = "ti,am654-cpsw-phy-sel";
-		reg= <0x0 0x40f04040 0x0 0x4>;
-		reg-names = "gmii-sel";
-	};
-};
-
-&wkup_i2c0_pins_default {
-	u-boot,dm-spl;
-};
-
-&wkup_i2c0 {
-	u-boot,dm-spl;
-};
-
-&main_i2c0 {
-	u-boot,dm-spl;
-};
-
-&main_i2c0_pins_default {
-	u-boot,dm-spl;
-};
-
-&exp2 {
-	u-boot,dm-spl;
-};
-
-&main_gpio0 {
-	u-boot,dm-spl;
-};
+// &main_usbss0_pins_default {
+// 	u-boot,dm-spl;
+// };
+
+// &usbss0 {
+// 	u-boot,dm-spl;
+// 	ti,usb2-only;
+// };
+
+// &usb0 {
+// 	dr_mode = "peripheral";
+// 	u-boot,dm-spl;
+// };
+
+// &mcu_cpsw {
+// 	pinctrl-names = "default";
+// 	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+// };
+
+// &davinci_mdio {
+// 	phy0: ethernet-phy@3 {
+// 		reg = <3>;
+// 		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+// 		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+// 	};
+// };
+
+// &cpsw_port1 {
+// 	phy-mode = "rgmii-rxid";
+// 	phy-handle = <&phy0>;
+// };
+
+// &mcu_cpsw {
+// 	reg = <0x0 0x46000000 0x0 0x200000>,
+// 	      <0x0 0x40f00200 0x0 0x2>;
+// 	reg-names = "cpsw_nuss", "mac_efuse";
+// 	/delete-property/ ranges;
+
+// 	cpsw-phy-sel@40f04040 {
+// 		compatible = "ti,am654-cpsw-phy-sel";
+// 		reg= <0x0 0x40f04040 0x0 0x4>;
+// 		reg-names = "gmii-sel";
+// 	};
+// };
+
+// &wkup_i2c0_pins_default {
+// 	u-boot,dm-spl;
+// };
+
+// &wkup_i2c0 {
+// 	u-boot,dm-spl;
+// };
+
+// &main_i2c0 {
+// 	u-boot,dm-spl;
+// };
+
+// &main_i2c0_pins_default {
+// 	u-boot,dm-spl;
+// };
+
+// &exp2 {
+// 	u-boot,dm-spl;
+// };
+
+// &main_gpio0 {
+// 	u-boot,dm-spl;
+// };
 
 &main_mmc1_pins_default {
 	u-boot,dm-spl;
@@ -221,31 +221,31 @@
 	u-boot,dm-spl;
 };
 
-&wiz3_pll1_refclk {
-	assigned-clocks = <&wiz3_pll1_refclk>, <&wiz3_pll0_refclk>;
-	assigned-clock-parents = <&k3_clks 295 0>, <&k3_clks 295 9>;
-};
+// &wiz3_pll1_refclk {
+// 	assigned-clocks = <&wiz3_pll1_refclk>, <&wiz3_pll0_refclk>;
+// 	assigned-clock-parents = <&k3_clks 295 0>, <&k3_clks 295 9>;
+// };
 
-&serdes_ln_ctrl {
-	u-boot,mux-autoprobe;
-};
+// &serdes_ln_ctrl {
+// 	u-boot,mux-autoprobe;
+// };
 
-&usb_serdes_mux {
-	u-boot,mux-autoprobe;
-};
+// &usb_serdes_mux {
+// 	u-boot,mux-autoprobe;
+// };
 
 &chipid {
 	u-boot,dm-spl;
 };
 
-&ospi1 {
-	u-boot,dm-spl;
+// &ospi1 {
+// 	u-boot,dm-spl;
 
-	flash@0 {
-		u-boot,dm-spl;
-	};
-};
+// 	flash@0 {
+// 		u-boot,dm-spl;
+// 	};
+// };
 
-&mcu_fss0_ospi1_pins_default {
-	u-boot,dm-spl;
-};
+// &mcu_fss0_ospi1_pins_default {
+// 	u-boot,dm-spl;
+// };
diff --git a/board-support/u-boot-2020.01+gitAUTOINC+3c9ebdb87d-g3c9ebdb87d/arch/arm/dts/k3-j721e-common-proc-board.dts b/board-support/u-boot-2020.01+gitAUTOINC+3c9ebdb87d-g3c9ebdb87d/arch/arm/dts/k3-j721e-common-proc-board.dts
index 15b33309a..3f585cc56 100644
--- a/board-support/u-boot-2020.01+gitAUTOINC+3c9ebdb87d-g3c9ebdb87d/arch/arm/dts/k3-j721e-common-proc-board.dts
+++ b/board-support/u-boot-2020.01+gitAUTOINC+3c9ebdb87d-g3c9ebdb87d/arch/arm/dts/k3-j721e-common-proc-board.dts
@@ -26,107 +26,107 @@
 		remoteproc8 = &c71_0;
 	};
 
-	evm_12v0: fixedregulator-evm12v0 {
-		/* main supply */
-		compatible = "regulator-fixed";
-		regulator-name = "evm_12v0";
-		regulator-min-microvolt = <12000000>;
-		regulator-max-microvolt = <12000000>;
-		regulator-always-on;
-		regulator-boot-on;
-		u-boot,dm-spl;
-	};
-
-	vsys_3v3: fixedregulator-vsys3v3 {
-		/* Output of LMS140 */
-		compatible = "regulator-fixed";
-		regulator-name = "vsys_3v3";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		vin-supply = <&evm_12v0>;
-		regulator-always-on;
-		regulator-boot-on;
-		u-boot,dm-spl;
-	};
-
-	vsys_5v0: fixedregulator-vsys5v0 {
-		/* Output of LM5140 */
-		compatible = "regulator-fixed";
-		regulator-name = "vsys_5v0";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&evm_12v0>;
-		regulator-always-on;
-		regulator-boot-on;
-		u-boot,dm-spl;
-	};
-
-	vdd_mmc1: fixedregulator-sd {
-		compatible = "regulator-fixed";
-		regulator-name = "vdd_mmc1";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		enable-active-high;
-		vin-supply = <&vsys_3v3>;
-		gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
-		u-boot,dm-spl;
-	};
-
-	vdd_sd_dv_alt: gpio-regulator-TLV71033 {
-		compatible = "regulator-gpio";
-		pinctrl-names = "default";
-		pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
-		regulator-name = "tlv71033";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		u-boot,dm-spl;
-		vin-supply = <&vsys_5v0>;
-		gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>;
-		states = <1800000 0x0
-			  3300000 0x1>;
-	};
+	// evm_12v0: fixedregulator-evm12v0 {
+	// 	/* main supply */
+	// 	compatible = "regulator-fixed";
+	// 	regulator-name = "evm_12v0";
+	// 	regulator-min-microvolt = <12000000>;
+	// 	regulator-max-microvolt = <12000000>;
+	// 	regulator-always-on;
+	// 	regulator-boot-on;
+	// 	u-boot,dm-spl;
+	// };
+
+	// vsys_3v3: fixedregulator-vsys3v3 {
+	// 	/* Output of LMS140 */
+	// 	compatible = "regulator-fixed";
+	// 	regulator-name = "vsys_3v3";
+	// 	regulator-min-microvolt = <3300000>;
+	// 	regulator-max-microvolt = <3300000>;
+	// 	vin-supply = <&evm_12v0>;
+	// 	regulator-always-on;
+	// 	regulator-boot-on;
+	// 	u-boot,dm-spl;
+	// };
+
+	// vsys_5v0: fixedregulator-vsys5v0 {
+	// 	/* Output of LM5140 */
+	// 	compatible = "regulator-fixed";
+	// 	regulator-name = "vsys_5v0";
+	// 	regulator-min-microvolt = <5000000>;
+	// 	regulator-max-microvolt = <5000000>;
+	// 	vin-supply = <&evm_12v0>;
+	// 	regulator-always-on;
+	// 	regulator-boot-on;
+	// 	u-boot,dm-spl;
+	// };
+
+	// vdd_mmc1: fixedregulator-sd {
+	// 	compatible = "regulator-fixed";
+	// 	regulator-name = "vdd_mmc1";
+	// 	regulator-min-microvolt = <3300000>;
+	// 	regulator-max-microvolt = <3300000>;
+	// 	regulator-boot-on;
+	// 	enable-active-high;
+	// 	vin-supply = <&vsys_3v3>;
+	// 	gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
+	// 	u-boot,dm-spl;
+	// };
+
+	// vdd_sd_dv_alt: gpio-regulator-TLV71033 {
+	// 	compatible = "regulator-gpio";
+	// 	pinctrl-names = "default";
+	// 	pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
+	// 	regulator-name = "tlv71033";
+	// 	regulator-min-microvolt = <1800000>;
+	// 	regulator-max-microvolt = <3300000>;
+	// 	regulator-boot-on;
+	// 	u-boot,dm-spl;
+	// 	vin-supply = <&vsys_5v0>;
+	// 	gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>;
+	// 	states = <1800000 0x0
+	// 		  3300000 0x1>;
+	// };
 };
 
-&wkup_uart0 {
-	/* Wakeup UART is used by System firmware */
-	status = "disabled";
-};
+// &wkup_uart0 {
+// 	/* Wakeup UART is used by System firmware */
+// 	status = "disabled";
+// };
 
 &main_uart0 {
 	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
 };
 
-&main_uart3 {
-	/* UART not brought out */
-	status = "disabled";
-};
+// &main_uart3 {
+// 	/* UART not brought out */
+// 	status = "disabled";
+// };
 
-&main_uart5 {
-	/* UART not brought out */
-	status = "disabled";
-};
+// &main_uart5 {
+// 	/* UART not brought out */
+// 	status = "disabled";
+// };
 
-&main_uart6 {
-	/* UART not brought out */
-	status = "disabled";
-};
+// &main_uart6 {
+// 	/* UART not brought out */
+// 	status = "disabled";
+// };
 
-&main_uart7 {
-	/* UART not brought out */
-	status = "disabled";
-};
+// &main_uart7 {
+// 	/* UART not brought out */
+// 	status = "disabled";
+// };
 
-&main_uart8 {
-	/* UART not brought out */
-	status = "disabled";
-};
+// &main_uart8 {
+// 	/* UART not brought out */
+// 	status = "disabled";
+// };
 
-&main_uart9 {
-	/* UART not brought out */
-	status = "disabled";
-};
+// &main_uart9 {
+// 	/* UART not brought out */
+// 	status = "disabled";
+// };
 
 &main_pmx0 {
 	main_mmc1_pins_default: main_mmc1_pins_default {
@@ -143,12 +143,12 @@
 		>;
 	};
 
-	vdd_sd_dv_alt_pins_default: vdd_sd_dv_alt_pins_default {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */
-		>;
-		u-boot,dm-spl;
-	};
+	// vdd_sd_dv_alt_pins_default: vdd_sd_dv_alt_pins_default {
+	// 	pinctrl-single,pins = <
+	// 		J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */
+	// 	>;
+	// 	u-boot,dm-spl;
+	// };
 };
 
 &main_sdhci0 {
@@ -162,146 +162,146 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&main_mmc1_pins_default>;
 	ti,driver-strength-ohm = <50>;
-	vmmc-supply = <&vdd_mmc1>;
-	vqmmc-supply = <&vdd_sd_dv_alt>;
+	// vmmc-supply = <&vdd_mmc1>;
+	// vqmmc-supply = <&vdd_sd_dv_alt>;
 };
 
-&wkup_pmx0 {
-	wkup_i2c0_pins_default: wkup-i2c0-pins-default {
-		pinctrl-single,pins = <
-			J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
-			J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
-		>;
-	};
-
-	mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
-		pinctrl-single,pins = <
-			J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */
-			J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */
-			J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */
-			J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */
-			J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */
-			J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */
-			J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */
-			J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */
-		>;
-	};
-};
-
-&main_pmx0 {
-	main_usbss0_pins_default: main_usbss0_pins_default {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
-			J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
-		>;
-	};
-
-	main_usbss1_pins_default: main_usbss1_pins_default {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
-		>;
-	};
-
-	main_i2c0_pins_default: main-i2c0-pins-default {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
-			J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
-		>;
-	};
-};
-
-&wkup_i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&wkup_i2c0_pins_default>;
-	clock-frequency = <400000>;
-};
-
-&usbss0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_usbss0_pins_default>;
-	ti,vbus-divider;
-};
-
-&usb0 {
-	dr_mode = "otg";
-	maximum-speed = "super-speed";
-	phys = <&serdes3_usb_link>;
-	phy-names = "cdns3,usb3-phy";
-};
-
-&usbss1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_usbss1_pins_default>;
-	ti,usb2-only;
-};
-
-&usb1 {
-	dr_mode = "host";
-	maximum-speed = "high-speed";
-};
-
-&main_i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_i2c0_pins_default>;
-	clock-frequency = <400000>;
-
-	exp1: gpio@20 {
-		compatible = "ti,tca6416";
-		reg = <0x20>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
-
-	exp2: gpio@22 {
-		compatible = "ti,tca6424";
-		reg = <0x22>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
-};
-
-&ospi1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
-
-	flash@0{
-		compatible = "jedec,spi-nor";
-		reg = <0x0>;
-		spi-tx-bus-width = <1>;
-		spi-rx-bus-width = <4>;
-		spi-max-frequency = <40000000>;
-		cdns,tshsl-ns = <60>;
-		cdns,tsd2d-ns = <60>;
-		cdns,tchsh-ns = <60>;
-		cdns,tslch-ns = <60>;
-		cdns,read-delay = <2>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-	};
-};
-
-&usb_serdes_mux {
-	idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */
-};
-
-&serdes_ln_ctrl {
-	idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
-		      <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
-		      <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
-		      <SERDES3_LANE0_USB3_0_SWAP>, <SERDES3_LANE1_USB3_0>,
-		      <SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
-};
-
-&serdes_wiz3 {
-	typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
-};
-
-&serdes3 {
-	serdes3_usb_link: link@0 {
-		reg = <0>;
-		cdns,num-lanes = <2>;
-		#phy-cells = <0>;
-		cdns,phy-type = <PHY_TYPE_USB3>;
-		resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
-	};
-};
+// &wkup_pmx0 {
+// 	wkup_i2c0_pins_default: wkup-i2c0-pins-default {
+// 		pinctrl-single,pins = <
+// 			J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
+// 			J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
+// 		>;
+// 	};
+
+// 	mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
+// 		pinctrl-single,pins = <
+// 			J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */
+// 			J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */
+// 			J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */
+// 			J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */
+// 			J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */
+// 			J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */
+// 			J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */
+// 			J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */
+// 		>;
+// 	};
+// };
+
+// &main_pmx0 {
+// 	main_usbss0_pins_default: main_usbss0_pins_default {
+// 		pinctrl-single,pins = <
+// 			J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
+// 			J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
+// 		>;
+// 	};
+
+// 	main_usbss1_pins_default: main_usbss1_pins_default {
+// 		pinctrl-single,pins = <
+// 			J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
+// 		>;
+// 	};
+
+// 	main_i2c0_pins_default: main-i2c0-pins-default {
+// 		pinctrl-single,pins = <
+// 			J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
+// 			J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
+// 		>;
+// 	};
+// };
+
+// &wkup_i2c0 {
+// 	pinctrl-names = "default";
+// 	pinctrl-0 = <&wkup_i2c0_pins_default>;
+// 	clock-frequency = <400000>;
+// };
+
+// &usbss0 {
+// 	pinctrl-names = "default";
+// 	pinctrl-0 = <&main_usbss0_pins_default>;
+// 	ti,vbus-divider;
+// };
+
+// &usb0 {
+// 	dr_mode = "otg";
+// 	maximum-speed = "super-speed";
+// 	phys = <&serdes3_usb_link>;
+// 	phy-names = "cdns3,usb3-phy";
+// };
+
+// &usbss1 {
+// 	pinctrl-names = "default";
+// 	pinctrl-0 = <&main_usbss1_pins_default>;
+// 	ti,usb2-only;
+// };
+
+// &usb1 {
+// 	dr_mode = "host";
+// 	maximum-speed = "high-speed";
+// };
+
+// &main_i2c0 {
+// 	pinctrl-names = "default";
+// 	pinctrl-0 = <&main_i2c0_pins_default>;
+// 	clock-frequency = <400000>;
+
+// 	exp1: gpio@20 {
+// 		compatible = "ti,tca6416";
+// 		reg = <0x20>;
+// 		gpio-controller;
+// 		#gpio-cells = <2>;
+// 	};
+
+// 	exp2: gpio@22 {
+// 		compatible = "ti,tca6424";
+// 		reg = <0x22>;
+// 		gpio-controller;
+// 		#gpio-cells = <2>;
+// 	};
+// };
+
+// &ospi1 {
+// 	pinctrl-names = "default";
+// 	pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
+
+// 	flash@0{
+// 		compatible = "jedec,spi-nor";
+// 		reg = <0x0>;
+// 		spi-tx-bus-width = <1>;
+// 		spi-rx-bus-width = <4>;
+// 		spi-max-frequency = <40000000>;
+// 		cdns,tshsl-ns = <60>;
+// 		cdns,tsd2d-ns = <60>;
+// 		cdns,tchsh-ns = <60>;
+// 		cdns,tslch-ns = <60>;
+// 		cdns,read-delay = <2>;
+// 		#address-cells = <1>;
+// 		#size-cells = <1>;
+// 	};
+// };
+
+// &usb_serdes_mux {
+// 	idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */
+// };
+
+// &serdes_ln_ctrl {
+// 	idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
+// 		      <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
+// 		      <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
+// 		      <SERDES3_LANE0_USB3_0_SWAP>, <SERDES3_LANE1_USB3_0>,
+// 		      <SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
+// };
+
+// &serdes_wiz3 {
+// 	typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
+// };
+
+// &serdes3 {
+// 	serdes3_usb_link: link@0 {
+// 		reg = <0>;
+// 		cdns,num-lanes = <2>;
+// 		#phy-cells = <0>;
+// 		cdns,phy-type = <PHY_TYPE_USB3>;
+// 		resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
+// 	};
+// };
diff --git a/board-support/u-boot-2020.01+gitAUTOINC+3c9ebdb87d-g3c9ebdb87d/arch/arm/dts/k3-j721e-main.dtsi b/board-support/u-boot-2020.01+gitAUTOINC+3c9ebdb87d-g3c9ebdb87d/arch/arm/dts/k3-j721e-main.dtsi
index f6b6446d6..54a724c7e 100644
--- a/board-support/u-boot-2020.01+gitAUTOINC+3c9ebdb87d-g3c9ebdb87d/arch/arm/dts/k3-j721e-main.dtsi
+++ b/board-support/u-boot-2020.01+gitAUTOINC+3c9ebdb87d-g3c9ebdb87d/arch/arm/dts/k3-j721e-main.dtsi
@@ -28,28 +28,28 @@
 		#size-cells = <1>;
 		ranges = <0x0 0x0 0x00100000 0x1c000>;
 
-		serdes_ln_ctrl: serdes_ln_ctrl@4080 {
-			compatible = "mmio-mux";
-			#mux-control-cells = <1>;
-			mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
-					<0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
-					<0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
-					<0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
-					<0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
-					/* SERDES4 lane0/1/2/3 select */
-			idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
-				      <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
-				      <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
-				      <MUX_IDLE_AS_IS>, <SERDES3_LANE1_USB3_0>,
-				      <SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
-		};
-
-		usb_serdes_mux: mux-controller@4000 {
-			compatible = "mmio-mux";
-			#mux-control-cells = <1>;
-			mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
-					<0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */
-	    };
+		// serdes_ln_ctrl: serdes_ln_ctrl@4080 {
+		// 	compatible = "mmio-mux";
+		// 	#mux-control-cells = <1>;
+		// 	mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
+		// 			<0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
+		// 			<0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
+		// 			<0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
+		// 			<0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
+		// 			/* SERDES4 lane0/1/2/3 select */
+		// 	idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
+		// 		      <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
+		// 		      <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
+		// 		      <MUX_IDLE_AS_IS>, <SERDES3_LANE1_USB3_0>,
+		// 		      <SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
+		// };
+
+		// usb_serdes_mux: mux-controller@4000 {
+		// 	compatible = "mmio-mux";
+		// 	#mux-control-cells = <1>;
+		// 	mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
+		// 			<0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */
+	    // };
 	};
 
 	gic500: interrupt-controller@1800000 {
@@ -116,67 +116,67 @@
 		clock-frequency = <0>;
 	};
 
-	serdes_wiz3: wiz@5030000 {
-		compatible = "ti,j721e-wiz";
-		#address-cells = <2>;
-		#size-cells = <2>;
-		power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&dummy_cmn_refclk>;
-		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
-		assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
-		assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
-		num-lanes = <2>;
-		#reset-cells = <1>;
-		ranges;
-
-		wiz3_pll0_refclk: pll0_refclk {
-			clocks = <&k3_clks 295 9>, <&dummy_cmn_refclk>;
-			clock-output-names = "wiz3_pll0_refclk";
-			#clock-cells = <0>;
-			assigned-clocks = <&wiz3_pll0_refclk>;
-			assigned-clock-parents = <&k3_clks 295 9>;
-		};
-
-		wiz3_pll1_refclk: pll1_refclk {
-			clocks = <&k3_clks 295 0>, <&dummy_cmn_refclk1>;
-			clock-output-names = "wiz3_pll1_refclk";
-			#clock-cells = <0>;
-			assigned-clocks = <&wiz3_pll1_refclk>;
-			assigned-clock-parents = <&k3_clks 295 0>;
-		};
-
-		wiz3_refclk_dig: refclk_dig {
-			clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
-			clock-output-names = "wiz3_refclk_dig";
-			#clock-cells = <0>;
-			assigned-clocks = <&wiz3_refclk_dig>;
-			assigned-clock-parents = <&k3_clks 295 9>;
-		};
-
-		wiz3_cmn_refclk: cmn_refclk {
-			clocks = <&wiz3_refclk_dig>;
-			clock-output-names = "wiz3_cmn_refclk";
-			#clock-cells = <0>;
-		};
-
-		wiz3_cmn_refclk1: cmn_refclk1 {
-			clocks = <&wiz3_pll1_refclk>;
-			clock-output-names = "wiz3_cmn_refclk1";
-			#clock-cells = <0>;
-		};
-
-		serdes3: serdes@5030000 {
-			compatible = "cdns,ti,sierra-phy-t0";
-			reg-names = "serdes";
-			reg = <0x00 0x5030000 0x00 0x10000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			resets = <&serdes_wiz3 0>;
-			reset-names = "sierra_reset";
-			clocks = <&wiz3_cmn_refclk>, <&wiz3_cmn_refclk1>;
-			clock-names = "cmn_refclk", "cmn_refclk1";
-		};
-	};
+	// serdes_wiz3: wiz@5030000 {
+	// 	compatible = "ti,j721e-wiz";
+	// 	#address-cells = <2>;
+	// 	#size-cells = <2>;
+	// 	power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&dummy_cmn_refclk>;
+	// 	clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+	// 	assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
+	// 	assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
+	// 	num-lanes = <2>;
+	// 	#reset-cells = <1>;
+	// 	ranges;
+
+	// 	wiz3_pll0_refclk: pll0_refclk {
+	// 		clocks = <&k3_clks 295 9>, <&dummy_cmn_refclk>;
+	// 		clock-output-names = "wiz3_pll0_refclk";
+	// 		#clock-cells = <0>;
+	// 		assigned-clocks = <&wiz3_pll0_refclk>;
+	// 		assigned-clock-parents = <&k3_clks 295 9>;
+	// 	};
+
+	// 	wiz3_pll1_refclk: pll1_refclk {
+	// 		clocks = <&k3_clks 295 0>, <&dummy_cmn_refclk1>;
+	// 		clock-output-names = "wiz3_pll1_refclk";
+	// 		#clock-cells = <0>;
+	// 		assigned-clocks = <&wiz3_pll1_refclk>;
+	// 		assigned-clock-parents = <&k3_clks 295 0>;
+	// 	};
+
+	// 	wiz3_refclk_dig: refclk_dig {
+	// 		clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
+	// 		clock-output-names = "wiz3_refclk_dig";
+	// 		#clock-cells = <0>;
+	// 		assigned-clocks = <&wiz3_refclk_dig>;
+	// 		assigned-clock-parents = <&k3_clks 295 9>;
+	// 	};
+
+	// 	wiz3_cmn_refclk: cmn_refclk {
+	// 		clocks = <&wiz3_refclk_dig>;
+	// 		clock-output-names = "wiz3_cmn_refclk";
+	// 		#clock-cells = <0>;
+	// 	};
+
+	// 	wiz3_cmn_refclk1: cmn_refclk1 {
+	// 		clocks = <&wiz3_pll1_refclk>;
+	// 		clock-output-names = "wiz3_cmn_refclk1";
+	// 		#clock-cells = <0>;
+	// 	};
+
+	// 	serdes3: serdes@5030000 {
+	// 		compatible = "cdns,ti,sierra-phy-t0";
+	// 		reg-names = "serdes";
+	// 		reg = <0x00 0x5030000 0x00 0x10000>;
+	// 		#address-cells = <1>;
+	// 		#size-cells = <0>;
+	// 		resets = <&serdes_wiz3 0>;
+	// 		reset-names = "sierra_reset";
+	// 		clocks = <&wiz3_cmn_refclk>, <&wiz3_cmn_refclk1>;
+	// 		clock-names = "cmn_refclk", "cmn_refclk1";
+	// 	};
+	// };
 
 	main_uart0: serial@2800000 {
 		compatible = "ti,j721e-uart", "ti,am654-uart";
@@ -191,161 +191,161 @@
 		clock-names = "fclk";
 	};
 
-	main_uart1: serial@2810000 {
-		compatible = "ti,j721e-uart", "ti,am654-uart";
-		reg = <0x00 0x02810000 0x00 0x100>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <48000000>;
-		current-speed = <115200>;
-		power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 278 0>;
-		clock-names = "fclk";
-	};
-
-	main_uart2: serial@2820000 {
-		compatible = "ti,j721e-uart", "ti,am654-uart";
-		reg = <0x00 0x02820000 0x00 0x100>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <48000000>;
-		current-speed = <115200>;
-		power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 279 0>;
-		clock-names = "fclk";
-	};
-
-	main_uart3: serial@2830000 {
-		compatible = "ti,j721e-uart", "ti,am654-uart";
-		reg = <0x00 0x02830000 0x00 0x100>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <48000000>;
-		current-speed = <115200>;
-		power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 280 0>;
-		clock-names = "fclk";
-	};
-
-	main_uart4: serial@2840000 {
-		compatible = "ti,j721e-uart", "ti,am654-uart";
-		reg = <0x00 0x02840000 0x00 0x100>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <48000000>;
-		current-speed = <115200>;
-		power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 281 0>;
-		clock-names = "fclk";
-	};
-
-	main_uart5: serial@2850000 {
-		compatible = "ti,j721e-uart", "ti,am654-uart";
-		reg = <0x00 0x02850000 0x00 0x100>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <48000000>;
-		current-speed = <115200>;
-		power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 282 0>;
-		clock-names = "fclk";
-	};
-
-	main_uart6: serial@2860000 {
-		compatible = "ti,j721e-uart", "ti,am654-uart";
-		reg = <0x00 0x02860000 0x00 0x100>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <48000000>;
-		current-speed = <115200>;
-		power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 283 0>;
-		clock-names = "fclk";
-	};
-
-	main_uart7: serial@2870000 {
-		compatible = "ti,j721e-uart", "ti,am654-uart";
-		reg = <0x00 0x02870000 0x00 0x100>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <48000000>;
-		current-speed = <115200>;
-		power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 284 0>;
-		clock-names = "fclk";
-	};
-
-	main_uart8: serial@2880000 {
-		compatible = "ti,j721e-uart", "ti,am654-uart";
-		reg = <0x00 0x02880000 0x00 0x100>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <48000000>;
-		current-speed = <115200>;
-		power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 285 0>;
-		clock-names = "fclk";
-	};
-
-	main_uart9: serial@2890000 {
-		compatible = "ti,j721e-uart", "ti,am654-uart";
-		reg = <0x00 0x02890000 0x00 0x100>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <48000000>;
-		current-speed = <115200>;
-		power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 286 0>;
-		clock-names = "fclk";
-	};
-
-	main_gpio0: gpio@600000 {
-		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
-		reg = <0x0 0x00600000 0x0 0x100>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		interrupts = <105 0 IRQ_TYPE_EDGE_RISING>,
-			     <105 1 IRQ_TYPE_EDGE_RISING>,
-			     <105 2 IRQ_TYPE_EDGE_RISING>,
-			     <105 3 IRQ_TYPE_EDGE_RISING>,
-			     <105 4 IRQ_TYPE_EDGE_RISING>,
-			     <105 5 IRQ_TYPE_EDGE_RISING>,
-			     <105 6 IRQ_TYPE_EDGE_RISING>,
-			     <105 7 IRQ_TYPE_EDGE_RISING>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		ti,ngpio = <128>;
-		ti,davinci-gpio-unbanked = <0>;
-		power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 105 0>;
-		clock-names = "gpio";
-	};
-
-	main_gpio1: gpio@601000 {
-		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
-		reg = <0x0 0x00601000 0x0 0x100>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		interrupts = <106 0 IRQ_TYPE_EDGE_RISING>,
-			     <106 1 IRQ_TYPE_EDGE_RISING>,
-			     <106 2 IRQ_TYPE_EDGE_RISING>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		ti,ngpio = <36>;
-		ti,davinci-gpio-unbanked = <0>;
-		power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 106 0>;
-		clock-names = "gpio";
-	};
+	// main_uart1: serial@2810000 {
+	// 	compatible = "ti,j721e-uart", "ti,am654-uart";
+	// 	reg = <0x00 0x02810000 0x00 0x100>;
+	// 	reg-shift = <2>;
+	// 	reg-io-width = <4>;
+	// 	interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+	// 	clock-frequency = <48000000>;
+	// 	current-speed = <115200>;
+	// 	power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 278 0>;
+	// 	clock-names = "fclk";
+	// };
+
+	// main_uart2: serial@2820000 {
+	// 	compatible = "ti,j721e-uart", "ti,am654-uart";
+	// 	reg = <0x00 0x02820000 0x00 0x100>;
+	// 	reg-shift = <2>;
+	// 	reg-io-width = <4>;
+	// 	interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+	// 	clock-frequency = <48000000>;
+	// 	current-speed = <115200>;
+	// 	power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 279 0>;
+	// 	clock-names = "fclk";
+	// };
+
+	// main_uart3: serial@2830000 {
+	// 	compatible = "ti,j721e-uart", "ti,am654-uart";
+	// 	reg = <0x00 0x02830000 0x00 0x100>;
+	// 	reg-shift = <2>;
+	// 	reg-io-width = <4>;
+	// 	interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
+	// 	clock-frequency = <48000000>;
+	// 	current-speed = <115200>;
+	// 	power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 280 0>;
+	// 	clock-names = "fclk";
+	// };
+
+	// main_uart4: serial@2840000 {
+	// 	compatible = "ti,j721e-uart", "ti,am654-uart";
+	// 	reg = <0x00 0x02840000 0x00 0x100>;
+	// 	reg-shift = <2>;
+	// 	reg-io-width = <4>;
+	// 	interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
+	// 	clock-frequency = <48000000>;
+	// 	current-speed = <115200>;
+	// 	power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 281 0>;
+	// 	clock-names = "fclk";
+	// };
+
+	// main_uart5: serial@2850000 {
+	// 	compatible = "ti,j721e-uart", "ti,am654-uart";
+	// 	reg = <0x00 0x02850000 0x00 0x100>;
+	// 	reg-shift = <2>;
+	// 	reg-io-width = <4>;
+	// 	interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+	// 	clock-frequency = <48000000>;
+	// 	current-speed = <115200>;
+	// 	power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 282 0>;
+	// 	clock-names = "fclk";
+	// };
+
+	// main_uart6: serial@2860000 {
+	// 	compatible = "ti,j721e-uart", "ti,am654-uart";
+	// 	reg = <0x00 0x02860000 0x00 0x100>;
+	// 	reg-shift = <2>;
+	// 	reg-io-width = <4>;
+	// 	interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
+	// 	clock-frequency = <48000000>;
+	// 	current-speed = <115200>;
+	// 	power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 283 0>;
+	// 	clock-names = "fclk";
+	// };
+
+	// main_uart7: serial@2870000 {
+	// 	compatible = "ti,j721e-uart", "ti,am654-uart";
+	// 	reg = <0x00 0x02870000 0x00 0x100>;
+	// 	reg-shift = <2>;
+	// 	reg-io-width = <4>;
+	// 	interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+	// 	clock-frequency = <48000000>;
+	// 	current-speed = <115200>;
+	// 	power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 284 0>;
+	// 	clock-names = "fclk";
+	// };
+
+	// main_uart8: serial@2880000 {
+	// 	compatible = "ti,j721e-uart", "ti,am654-uart";
+	// 	reg = <0x00 0x02880000 0x00 0x100>;
+	// 	reg-shift = <2>;
+	// 	reg-io-width = <4>;
+	// 	interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
+	// 	clock-frequency = <48000000>;
+	// 	current-speed = <115200>;
+	// 	power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 285 0>;
+	// 	clock-names = "fclk";
+	// };
+
+	// main_uart9: serial@2890000 {
+	// 	compatible = "ti,j721e-uart", "ti,am654-uart";
+	// 	reg = <0x00 0x02890000 0x00 0x100>;
+	// 	reg-shift = <2>;
+	// 	reg-io-width = <4>;
+	// 	interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
+	// 	clock-frequency = <48000000>;
+	// 	current-speed = <115200>;
+	// 	power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 286 0>;
+	// 	clock-names = "fclk";
+	// };
+
+	// main_gpio0: gpio@600000 {
+	// 	compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+	// 	reg = <0x0 0x00600000 0x0 0x100>;
+	// 	gpio-controller;
+	// 	#gpio-cells = <2>;
+	// 	interrupts = <105 0 IRQ_TYPE_EDGE_RISING>,
+	// 		     <105 1 IRQ_TYPE_EDGE_RISING>,
+	// 		     <105 2 IRQ_TYPE_EDGE_RISING>,
+	// 		     <105 3 IRQ_TYPE_EDGE_RISING>,
+	// 		     <105 4 IRQ_TYPE_EDGE_RISING>,
+	// 		     <105 5 IRQ_TYPE_EDGE_RISING>,
+	// 		     <105 6 IRQ_TYPE_EDGE_RISING>,
+	// 		     <105 7 IRQ_TYPE_EDGE_RISING>;
+	// 	interrupt-controller;
+	// 	#interrupt-cells = <2>;
+	// 	ti,ngpio = <128>;
+	// 	ti,davinci-gpio-unbanked = <0>;
+	// 	power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 105 0>;
+	// 	clock-names = "gpio";
+	// };
+
+	// main_gpio1: gpio@601000 {
+	// 	compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+	// 	reg = <0x0 0x00601000 0x0 0x100>;
+	// 	gpio-controller;
+	// 	#gpio-cells = <2>;
+	// 	interrupts = <106 0 IRQ_TYPE_EDGE_RISING>,
+	// 		     <106 1 IRQ_TYPE_EDGE_RISING>,
+	// 		     <106 2 IRQ_TYPE_EDGE_RISING>;
+	// 	interrupt-controller;
+	// 	#interrupt-cells = <2>;
+	// 	ti,ngpio = <36>;
+	// 	ti,davinci-gpio-unbanked = <0>;
+	// 	power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 106 0>;
+	// 	clock-names = "gpio";
+	// };
 
 	main_sdhci0: sdhci@4f80000 {
 		compatible = "ti,j721e-sdhci-8bit";
@@ -365,10 +365,10 @@
 		mmc-hs400-1_8v;
 		sdhci-caps-mask = <0x2 0x0>;
 		ti,otap-del-sel-legacy = <0x0>;
-		ti,otap-del-sel-mmc-hs = <0x0>;
-		ti,otap-del-sel-ddr52 = <0x5>;
-		ti,otap-del-sel-hs200 = <0x2>;
-		ti,otap-del-sel-hs400 = <0x2>;
+		// ti,otap-del-sel-mmc-hs = <0x0>;
+		// ti,otap-del-sel-ddr52 = <0x5>;
+		// ti,otap-del-sel-hs200 = <0x2>;
+		// ti,otap-del-sel-hs400 = <0x2>;
 	};
 
 	main_sdhci1: sdhci@4fb0000 {
@@ -381,12 +381,12 @@
 		assigned-clocks = <&k3_clks 92 0>;
 		assigned-clock-parents = <&k3_clks 92 1>;
 		ti,otap-del-sel-legacy = <0x0>;
-		ti,otap-del-sel-sd-hs = <0xf>;
-		ti,otap-del-sel-sdr12 = <0xf>;
-		ti,otap-del-sel-sdr25 = <0xf>;
-		ti,otap-del-sel-sdr50 = <0xc>;
-		ti,otap-del-sel-sdr104 = <0x5>;
-		ti,otap-del-sel-ddr50 = <0xc>;
+		// ti,otap-del-sel-sd-hs = <0xf>;
+		// ti,otap-del-sel-sdr12 = <0xf>;
+		// ti,otap-del-sel-sdr25 = <0xf>;
+		// ti,otap-del-sel-sdr50 = <0xc>;
+		// ti,otap-del-sel-sdr104 = <0x5>;
+		// ti,otap-del-sel-ddr50 = <0xc>;
 		ti,trm-icp = <0x8>;
 		sdhci-caps-mask = <0x2 0x0>;
 		dma-coherent;
@@ -503,75 +503,75 @@
 		resets = <&k3_reset 15 1>;
 	};
 
-	usbss0: cdns_usb@4104000 {
-		compatible = "ti,j721e-usb";
-		reg = <0x00 0x4104000 0x00 0x100>;
-		dma-coherent;
-		power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
-		clock-names = "usb2_refclk", "lpm_clk";
-		assigned-clocks = <&k3_clks 288 15>;	/* USB2_REFCLK */
-		assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-
-		phy@4108000 {
-			compatible = "ti,j721e-usb2-phy";
-			reg = <0x00 0x4108000 0x00 0x400>;
-		};
-
-		usb0: usb@6000000 {
-			compatible = "cdns,usb3";
-			reg = <0x00 0x6000000 0x00 0x10000>,
-			      <0x00 0x6010000 0x00 0x10000>,
-			      <0x00 0x6020000 0x00 0x10000>;
-			reg-names = "otg", "xhci", "dev";
-			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,	/* irq.0 */
-				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,	/* irq.6 */
-				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;	/* otgirq.0 */
-			interrupt-names = "host",
-					  "peripheral",
-					  "otg";
-			maximum-speed = "super-speed";
-			dr_mode = "otg";
-		};
-	};
-
-	usbss1: cdns_usb@4114000 {
-		compatible = "ti,j721e-usb";
-		reg = <0x00 0x4114000 0x00 0x100>;
-		dma-coherent;
-		power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 289 15>, <&k3_clks 289 3>;
-		clock-names = "usb2_refclk", "lpm_clk";
-		assigned-clocks = <&k3_clks 289 15>;	/* USB2_REFCLK */
-		assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-
-		phy@4118000 {
-			compatible = "ti,j721e-usb2-phy";
-			reg = <0x00 0x4118000 0x00 0x400>;
-		};
-
-		usb1: usb@6400000 {
-			compatible = "cdns,usb3";
-			reg = <0x00 0x6400000 0x00 0x10000>,
-			      <0x00 0x6410000 0x00 0x10000>,
-			      <0x00 0x6420000 0x00 0x10000>;
-			reg-names = "otg", "xhci", "dev";
-			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,	/* irq.0 */
-				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,	/* irq.6 */
-				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;	/* otgirq.0 */
-			interrupt-names = "host",
-					  "peripheral",
-					  "otg";
-			maximum-speed = "super-speed";
-			dr_mode = "otg";
-		};
-	};
+	// usbss0: cdns_usb@4104000 {
+	// 	compatible = "ti,j721e-usb";
+	// 	reg = <0x00 0x4104000 0x00 0x100>;
+	// 	dma-coherent;
+	// 	power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
+	// 	clock-names = "usb2_refclk", "lpm_clk";
+	// 	assigned-clocks = <&k3_clks 288 15>;	/* USB2_REFCLK */
+	// 	assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
+	// 	#address-cells = <2>;
+	// 	#size-cells = <2>;
+	// 	ranges;
+
+	// 	phy@4108000 {
+	// 		compatible = "ti,j721e-usb2-phy";
+	// 		reg = <0x00 0x4108000 0x00 0x400>;
+	// 	};
+
+	// 	usb0: usb@6000000 {
+	// 		compatible = "cdns,usb3";
+	// 		reg = <0x00 0x6000000 0x00 0x10000>,
+	// 		      <0x00 0x6010000 0x00 0x10000>,
+	// 		      <0x00 0x6020000 0x00 0x10000>;
+	// 		reg-names = "otg", "xhci", "dev";
+	// 		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,	/* irq.0 */
+	// 			     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,	/* irq.6 */
+	// 			     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;	/* otgirq.0 */
+	// 		interrupt-names = "host",
+	// 				  "peripheral",
+	// 				  "otg";
+	// 		maximum-speed = "super-speed";
+	// 		dr_mode = "otg";
+	// 	};
+	// };
+
+	// usbss1: cdns_usb@4114000 {
+	// 	compatible = "ti,j721e-usb";
+	// 	reg = <0x00 0x4114000 0x00 0x100>;
+	// 	dma-coherent;
+	// 	power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 289 15>, <&k3_clks 289 3>;
+	// 	clock-names = "usb2_refclk", "lpm_clk";
+	// 	assigned-clocks = <&k3_clks 289 15>;	/* USB2_REFCLK */
+	// 	assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
+	// 	#address-cells = <2>;
+	// 	#size-cells = <2>;
+	// 	ranges;
+
+	// 	phy@4118000 {
+	// 		compatible = "ti,j721e-usb2-phy";
+	// 		reg = <0x00 0x4118000 0x00 0x400>;
+	// 	};
+
+	// 	usb1: usb@6400000 {
+	// 		compatible = "cdns,usb3";
+	// 		reg = <0x00 0x6400000 0x00 0x10000>,
+	// 		      <0x00 0x6410000 0x00 0x10000>,
+	// 		      <0x00 0x6420000 0x00 0x10000>;
+	// 		reg-names = "otg", "xhci", "dev";
+	// 		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,	/* irq.0 */
+	// 			     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,	/* irq.6 */
+	// 			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;	/* otgirq.0 */
+	// 		interrupt-names = "host",
+	// 				  "peripheral",
+	// 				  "otg";
+	// 		maximum-speed = "super-speed";
+	// 		dr_mode = "otg";
+	// 	};
+	// };
 
 	ufs_wrapper: ufs-wrapper@4e80000 {
 		compatible = "ti,j721e-ufs";
@@ -608,71 +608,71 @@
 		power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
 	};
 
-	main_i2c1: i2c@2010000 {
-		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
-		reg = <0x0 0x2010000 0x0 0x100>;
-		interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clock-names = "fck";
-		clocks = <&k3_clks 188 0>;
-		power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
-	};
-
-	main_i2c2: i2c@2020000 {
-		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
-		reg = <0x0 0x2020000 0x0 0x100>;
-		interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clock-names = "fck";
-		clocks = <&k3_clks 189 0>;
-		power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
-	};
-
-	main_i2c3: i2c@2030000 {
-		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
-		reg = <0x0 0x2030000 0x0 0x100>;
-		interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clock-names = "fck";
-		clocks = <&k3_clks 190 0>;
-		power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
-	};
-
-	main_i2c4: i2c@2040000 {
-		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
-		reg = <0x0 0x2040000 0x0 0x100>;
-		interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clock-names = "fck";
-		clocks = <&k3_clks 191 0>;
-		power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
-	};
-
-	main_i2c5: i2c@2050000 {
-		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
-		reg = <0x0 0x2050000 0x0 0x100>;
-		interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clock-names = "fck";
-		clocks = <&k3_clks 192 0>;
-		power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
-	};
-
-	main_i2c6: i2c@2060000 {
-		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
-		reg = <0x0 0x2060000 0x0 0x100>;
-		interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clock-names = "fck";
-		clocks = <&k3_clks 193 0>;
-		power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
-	};
+	// main_i2c1: i2c@2010000 {
+	// 	compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+	// 	reg = <0x0 0x2010000 0x0 0x100>;
+	// 	interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
+	// 	#address-cells = <1>;
+	// 	#size-cells = <0>;
+	// 	clock-names = "fck";
+	// 	clocks = <&k3_clks 188 0>;
+	// 	power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
+	// };
+
+	// main_i2c2: i2c@2020000 {
+	// 	compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+	// 	reg = <0x0 0x2020000 0x0 0x100>;
+	// 	interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
+	// 	#address-cells = <1>;
+	// 	#size-cells = <0>;
+	// 	clock-names = "fck";
+	// 	clocks = <&k3_clks 189 0>;
+	// 	power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
+	// };
+
+	// main_i2c3: i2c@2030000 {
+	// 	compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+	// 	reg = <0x0 0x2030000 0x0 0x100>;
+	// 	interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
+	// 	#address-cells = <1>;
+	// 	#size-cells = <0>;
+	// 	clock-names = "fck";
+	// 	clocks = <&k3_clks 190 0>;
+	// 	power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
+	// };
+
+	// main_i2c4: i2c@2040000 {
+	// 	compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+	// 	reg = <0x0 0x2040000 0x0 0x100>;
+	// 	interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
+	// 	#address-cells = <1>;
+	// 	#size-cells = <0>;
+	// 	clock-names = "fck";
+	// 	clocks = <&k3_clks 191 0>;
+	// 	power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
+	// };
+
+	// main_i2c5: i2c@2050000 {
+	// 	compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+	// 	reg = <0x0 0x2050000 0x0 0x100>;
+	// 	interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+	// 	#address-cells = <1>;
+	// 	#size-cells = <0>;
+	// 	clock-names = "fck";
+	// 	clocks = <&k3_clks 192 0>;
+	// 	power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
+	// };
+
+	// main_i2c6: i2c@2060000 {
+	// 	compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+	// 	reg = <0x0 0x2060000 0x0 0x100>;
+	// 	interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
+	// 	#address-cells = <1>;
+	// 	#size-cells = <0>;
+	// 	clock-names = "fck";
+	// 	clocks = <&k3_clks 193 0>;
+	// 	power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
+	// };
 
 	main_esm: esm@700000 {
 		compatible = "ti,j721e-esm";
diff --git a/board-support/u-boot-2020.01+gitAUTOINC+3c9ebdb87d-g3c9ebdb87d/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi b/board-support/u-boot-2020.01+gitAUTOINC+3c9ebdb87d-g3c9ebdb87d/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
index 439dbe158..af1e20e1b 100644
--- a/board-support/u-boot-2020.01+gitAUTOINC+3c9ebdb87d-g3c9ebdb87d/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
+++ b/board-support/u-boot-2020.01+gitAUTOINC+3c9ebdb87d-g3c9ebdb87d/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
@@ -58,29 +58,29 @@
 		pinctrl-single,function-mask = <0xffffffff>;
 	};
 
-	wkup_uart0: serial@42300000 {
-		compatible = "ti,j721e-uart", "ti,am654-uart";
-		reg = <0x00 0x42300000 0x00 0x100>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <48000000>;
-		current-speed = <115200>;
-		power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 287 0>;
-		clock-names = "fclk";
-	};
-
-	wkup_i2c0: i2c@42120000 {
-		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
-		reg = <0x0 0x42120000 0x0 0x100>;
-		interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clock-names = "fck";
-		clocks = <&k3_clks 197 0>;
-		power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
-	};
+	// wkup_uart0: serial@42300000 {
+	// 	compatible = "ti,j721e-uart", "ti,am654-uart";
+	// 	reg = <0x00 0x42300000 0x00 0x100>;
+	// 	reg-shift = <2>;
+	// 	reg-io-width = <4>;
+	// 	interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
+	// 	clock-frequency = <48000000>;
+	// 	current-speed = <115200>;
+	// 	power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
+	// 	clocks = <&k3_clks 287 0>;
+	// 	clock-names = "fclk";
+	// };
+
+	// wkup_i2c0: i2c@42120000 {
+	// 	compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+	// 	reg = <0x0 0x42120000 0x0 0x100>;
+	// 	interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
+	// 	#address-cells = <1>;
+	// 	#size-cells = <0>;
+	// 	clock-names = "fck";
+	// 	clocks = <&k3_clks 197 0>;
+	// 	power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
+	// };
 
 	mcu_uart0: serial@40a00000 {
 		compatible = "ti,j721e-uart", "ti,am654-uart";
@@ -140,23 +140,23 @@
 		#size-cells = <2>;
 		ranges;
 
-		hbmc_mux: hbmc-mux {
-			compatible = "mmio-mux";
-			#mux-control-cells = <1>;
-			mux-reg-masks = <0x4 0x2>; /* HBMC select */
-		};
-
-		hbmc: hyperbus@47034000 {
-			compatible = "ti,j721e-hbmc", "ti,am654-hbmc";
-			reg = <0x0 0x47034000 0x0 0x100>,
-				<0x5 0x00000000 0x1 0x0000000>;
-			power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
-			#address-cells = <2>;
-			#size-cells = <1>;
-			mux-controls = <&hbmc_mux 0>;
-			assigned-clocks = <&k3_clks 102 0>;
-			assigned-clock-rates = <250000000>;
-		};
+		// hbmc_mux: hbmc-mux {
+		// 	compatible = "mmio-mux";
+		// 	#mux-control-cells = <1>;
+		// 	mux-reg-masks = <0x4 0x2>; /* HBMC select */
+		// };
+
+		// hbmc: hyperbus@47034000 {
+		// 	compatible = "ti,j721e-hbmc", "ti,am654-hbmc";
+		// 	reg = <0x0 0x47034000 0x0 0x100>,
+		// 		<0x5 0x00000000 0x1 0x0000000>;
+		// 	power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
+		// 	#address-cells = <2>;
+		// 	#size-cells = <1>;
+		// 	mux-controls = <&hbmc_mux 0>;
+		// 	assigned-clocks = <&k3_clks 102 0>;
+		// 	assigned-clock-rates = <250000000>;
+		// };
 
 		ospi0: spi@47040000 {
 			compatible = "ti,am654-ospi";
@@ -175,21 +175,21 @@
 			#size-cells = <0>;
 		};
 
-		ospi1: spi@47050000 {
-			compatible = "ti,am654-ospi";
-			reg = <0x0 0x47050000 0x0 0x100>,
-				<0x7 0x00000000 0x1 0x00000000>;
-			interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
-			cdns,fifo-depth = <256>;
-			cdns,fifo-width = <4>;
-			cdns,trigger-address = <0x0>;
-			clocks = <&k3_clks 104 0>;
-			assigned-clocks = <&k3_clks 104 0>;
-			assigned-clock-rates = <133333333>;
-			power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
+		// ospi1: spi@47050000 {
+		// 	compatible = "ti,am654-ospi";
+		// 	reg = <0x0 0x47050000 0x0 0x100>,
+		// 		<0x7 0x00000000 0x1 0x00000000>;
+		// 	interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
+		// 	cdns,fifo-depth = <256>;
+		// 	cdns,fifo-width = <4>;
+		// 	cdns,trigger-address = <0x0>;
+		// 	clocks = <&k3_clks 104 0>;
+		// 	assigned-clocks = <&k3_clks 104 0>;
+		// 	assigned-clock-rates = <133333333>;
+		// 	power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
+		// 	#address-cells = <1>;
+		// 	#size-cells = <0>;
+		// };
 	};
 
 	mcu_i2c0: i2c@40b00000 {
@@ -203,16 +203,16 @@
 		power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
 	};
 
-	mcu_i2c1: i2c@40b10000 {
-		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
-		reg = <0x0 0x40b10000 0x0 0x100>;
-		interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clock-names = "fck";
-		clocks = <&k3_clks 195 0>;
-		power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
-	};
+	// mcu_i2c1: i2c@40b10000 {
+	// 	compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+	// 	reg = <0x0 0x40b10000 0x0 0x100>;
+	// 	interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
+	// 	#address-cells = <1>;
+	// 	#size-cells = <0>;
+	// 	clock-names = "fck";
+	// 	clocks = <&k3_clks 195 0>;
+	// 	power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
+	// };
 
 	chipid: chipid@43000014 {
 		compatible = "ti,am654-chipid";
@@ -262,63 +262,63 @@
 		};
 	};
 
-	mcu_cpsw: ethernet@46000000 {
-		compatible = "ti,j721e-cpsw-nuss";
-		#address-cells = <2>;
-		#size-cells = <2>;
-		reg = <0x0 0x46000000 0x0 0x200000>;
-		reg-names = "cpsw_nuss";
-		ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
-		dma-coherent;
-		clocks = <&k3_clks 18 22>;
-		clock-names = "fck";
-		power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
-
-		dmas = <&mcu_udmap 0xf000>,
-		       <&mcu_udmap 0xf001>,
-		       <&mcu_udmap 0xf002>,
-		       <&mcu_udmap 0xf003>,
-		       <&mcu_udmap 0xf004>,
-		       <&mcu_udmap 0xf005>,
-		       <&mcu_udmap 0xf006>,
-		       <&mcu_udmap 0xf007>,
-		       <&mcu_udmap 0x7000>;
-		dma-names = "tx0", "tx1", "tx2", "tx3",
-			    "tx4", "tx5", "tx6", "tx7",
-			    "rx";
-
-		ethernet-ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			cpsw_port1: port@1 {
-				reg = <1>;
-				ti,mac-only;
-				label = "port1";
-				ti,syscon-efuse = <&mcu_conf 0x200>;
-				phys = <&phy_gmii_sel 1>;
-			};
-		};
-
-		davinci_mdio: mdio@f00 {
-			compatible = "ti,cpsw-mdio","ti,davinci_mdio";
-			reg = <0x0 0xf00 0x0 0x100>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			clocks = <&k3_clks 18 22>;
-			clock-names = "fck";
-			bus_freq = <1000000>;
-		};
-
-		cpts@3d000 {
-			compatible = "ti,am65-cpts";
-			reg = <0x0 0x3d000 0x0 0x400>;
-			clocks = <&k3_clks 18 2>;
-			clock-names = "cpts";
-			interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "cpts";
-			ti,cpts-ext-ts-inputs = <4>;
-			ti,cpts-periodic-outputs = <2>;
-		};
-	};
+	// mcu_cpsw: ethernet@46000000 {
+	// 	compatible = "ti,j721e-cpsw-nuss";
+	// 	#address-cells = <2>;
+	// 	#size-cells = <2>;
+	// 	reg = <0x0 0x46000000 0x0 0x200000>;
+	// 	reg-names = "cpsw_nuss";
+	// 	ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
+	// 	dma-coherent;
+	// 	clocks = <&k3_clks 18 22>;
+	// 	clock-names = "fck";
+	// 	power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
+
+	// 	dmas = <&mcu_udmap 0xf000>,
+	// 	       <&mcu_udmap 0xf001>,
+	// 	       <&mcu_udmap 0xf002>,
+	// 	       <&mcu_udmap 0xf003>,
+	// 	       <&mcu_udmap 0xf004>,
+	// 	       <&mcu_udmap 0xf005>,
+	// 	       <&mcu_udmap 0xf006>,
+	// 	       <&mcu_udmap 0xf007>,
+	// 	       <&mcu_udmap 0x7000>;
+	// 	dma-names = "tx0", "tx1", "tx2", "tx3",
+	// 		    "tx4", "tx5", "tx6", "tx7",
+	// 		    "rx";
+
+	// 	ethernet-ports {
+	// 		#address-cells = <1>;
+	// 		#size-cells = <0>;
+
+	// 		cpsw_port1: port@1 {
+	// 			reg = <1>;
+	// 			ti,mac-only;
+	// 			label = "port1";
+	// 			ti,syscon-efuse = <&mcu_conf 0x200>;
+	// 			phys = <&phy_gmii_sel 1>;
+	// 		};
+	// 	};
+
+	// 	davinci_mdio: mdio@f00 {
+	// 		compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+	// 		reg = <0x0 0xf00 0x0 0x100>;
+	// 		#address-cells = <1>;
+	// 		#size-cells = <0>;
+	// 		clocks = <&k3_clks 18 22>;
+	// 		clock-names = "fck";
+	// 		bus_freq = <1000000>;
+	// 	};
+
+	// 	cpts@3d000 {
+	// 		compatible = "ti,am65-cpts";
+	// 		reg = <0x0 0x3d000 0x0 0x400>;
+	// 		clocks = <&k3_clks 18 2>;
+	// 		clock-names = "cpts";
+	// 		interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
+	// 		interrupt-names = "cpts";
+	// 		ti,cpts-ext-ts-inputs = <4>;
+	// 		ti,cpts-periodic-outputs = <2>;
+	// 	};
+	// };
 };
diff --git a/board-support/u-boot-2020.01+gitAUTOINC+3c9ebdb87d-g3c9ebdb87d/arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi b/board-support/u-boot-2020.01+gitAUTOINC+3c9ebdb87d-g3c9ebdb87d/arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi
index c6c60b44e..afb8cce4f 100644
--- a/board-support/u-boot-2020.01+gitAUTOINC+3c9ebdb87d-g3c9ebdb87d/arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi
+++ b/board-support/u-boot-2020.01+gitAUTOINC+3c9ebdb87d-g3c9ebdb87d/arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi
@@ -3,9 +3,9 @@
  * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
  */
 
-&tps659413a {
-	esm: esm {
-		compatible = "ti,tps659413-esm";
-		u-boot,dm-spl;
-	};
-};
+// &tps659413a {
+// 	esm: esm {
+// 		compatible = "ti,tps659413-esm";
+// 		u-boot,dm-spl;
+// 	};
+// };
diff --git a/board-support/u-boot-2020.01+gitAUTOINC+3c9ebdb87d-g3c9ebdb87d/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/board-support/u-boot-2020.01+gitAUTOINC+3c9ebdb87d-g3c9ebdb87d/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
index 8428c2bc9..dcc7cf0a5 100644
--- a/board-support/u-boot-2020.01+gitAUTOINC+3c9ebdb87d-g3c9ebdb87d/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
+++ b/board-support/u-boot-2020.01+gitAUTOINC+3c9ebdb87d-g3c9ebdb87d/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
@@ -139,16 +139,16 @@
 	};
 };
 
-&serdes0 {
-	serdes0_pcie_link: link@0 {
-		reg = <0>;
-		cdns,num-lanes = <1>;
-		#phy-cells = <0>;
-		cdns,phy-type = <PHY_TYPE_PCIE>;
-		resets = <&serdes_wiz0 1>;
-		u-boot,dm-spl;
-	};
-};
+// &serdes0 {
+// 	serdes0_pcie_link: link@0 {
+// 		reg = <0>;
+// 		cdns,num-lanes = <1>;
+// 		#phy-cells = <0>;
+// 		cdns,phy-type = <PHY_TYPE_PCIE>;
+// 		resets = <&serdes_wiz0 1>;
+// 		u-boot,dm-spl;
+// 	};
+// };
 
 &cbass_mcu_wakeup {
 	mcu_secproxy: secproxy@28380000 {
@@ -225,19 +225,19 @@
 		>;
 	};
 
-	mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
-		u-boot,dm-spl;
-		pinctrl-single,pins = <
-			J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */
-			J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */
-			J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */
-			J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */
-			J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */
-			J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */
-			J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */
-			J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */
-		>;
-	};
+	// mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
+	// 	u-boot,dm-spl;
+	// 	pinctrl-single,pins = <
+	// 		J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */
+	// 		J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */
+	// 		J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */
+	// 		J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */
+	// 		J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */
+	// 		J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */
+	// 		J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */
+	// 		J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */
+	// 	>;
+	// };
 };
 
 &main_pmx0 {
@@ -251,19 +251,19 @@
 		>;
 	};
 
-	main_usbss0_pins_default: main_usbss0_pins_default {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
-			J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
-		>;
-	};
+	// main_usbss0_pins_default: main_usbss0_pins_default {
+	// 	pinctrl-single,pins = <
+	// 		J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
+	// 		J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
+	// 	>;
+	// };
 
-	main_i2c0_pins_default: main-i2c0-pins-default {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
-			J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
-		>;
-	};
+	// main_i2c0_pins_default: main-i2c0-pins-default {
+	// 	pinctrl-single,pins = <
+	// 		J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
+	// 		J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
+	// 	>;
+	// };
 
 	main_mmc1_pins_default: main_mmc1_pins_default {
 		pinctrl-single,pins = <
@@ -280,22 +280,22 @@
 	};
 };
 
-&wkup_uart0 {
-	u-boot,dm-spl;
-	pinctrl-names = "default";
-	pinctrl-0 = <&wkup_uart0_pins_default>;
-	status = "okay";
-};
-
-&mcu_uart0 {
-	/delete-property/ power-domains;
-	/delete-property/ clocks;
-	/delete-property/ clock-names;
-	pinctrl-names = "default";
-	pinctrl-0 = <&mcu_uart0_pins_default>;
-	status = "okay";
-	clock-frequency = <48000000>;
-};
+// &wkup_uart0 {
+// 	u-boot,dm-spl;
+// 	pinctrl-names = "default";
+// 	pinctrl-0 = <&wkup_uart0_pins_default>;
+// 	status = "okay";
+// };
+
+// &mcu_uart0 {
+// 	/delete-property/ power-domains;
+// 	/delete-property/ clocks;
+// 	/delete-property/ clock-names;
+// 	pinctrl-names = "default";
+// 	pinctrl-0 = <&mcu_uart0_pins_default>;
+// 	status = "okay";
+// 	clock-frequency = <48000000>;
+// };
 
 &main_uart0 {
 	pinctrl-names = "default";
@@ -326,143 +326,143 @@
 	ti,driver-strength-ohm = <50>;
 };
 
-&wkup_i2c0 {
-	u-boot,dm-spl;
-	tps659413a: tps659413a@48 {
-		reg = <0x48>;
-		compatible = "ti,tps659413";
-		u-boot,dm-spl;
-		pinctrl-names = "default";
-		pinctrl-0 = <&wkup_i2c0_pins_default>;
-		clock-frequency = <400000>;
-
-		regulators: regulators {
-			u-boot,dm-spl;
-			buck12_reg: buck12 {
-				/*VDD_MPU*/
-				regulator-name = "buck12";
-				regulator-min-microvolt = <800000>;
-				regulator-max-microvolt = <1250000>;
-				regulator-always-on;
-				regulator-boot-on;
-				u-boot,dm-spl;
-			};
-		};
-	};
-
-	tps65917: tps65917@58 {
-		reg = <0x58>;
-		compatible = "ti,tps65917";
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		u-boot,dm-spl;
-
-		ti,system-power-controller;
-
-		tps65917_pmic {
-			compatible = "ti,tps65917-pmic";
-			u-boot,dm-spl;
-
-			tps65917_regulators: regulators {
-				u-boot,dm-spl;
-				smps12_reg: smps12 {
-					/* VDD_CPU_AVS_REG */
-					regulator-name = "smps1";
-					regulator-min-microvolt = <800000>;
-					regulator-max-microvolt = <1250000>;
-					regulator-always-on;
-					regulator-boot-on;
-					u-boot,dm-spl;
-				};
-
-				smps3_reg: smps3 {
-					/* V917_SMPS3_1V1 */
-					regulator-name = "smps3";
-					regulator-min-microvolt = <1100000>;
-					regulator-max-microvolt = <1100000>;
-					regulator-boot-on;
-					regulator-always-on;
-					u-boot,dm-spl;
-				};
-
-				smps4_reg: smps4 {
-					/* VDD_CORE_RAM_0V85_REG */
-					regulator-name = "smps4";
-					regulator-min-microvolt = <850000>;
-					regulator-max-microvolt = <850000>;
-					regulator-always-on;
-					regulator-boot-on;
-					u-boot,dm-spl;
-				};
-
-				smps5_reg: smps5 {
-					/* VDD_CPU_RAM_0V85_REG */
-					regulator-name = "smps5";
-					regulator-min-microvolt = <850000>;
-					regulator-max-microvolt = <850000>;
-					regulator-boot-on;
-					regulator-always-on;
-					u-boot,dm-spl;
-				};
-
-				ldo1_reg: ldo1 {
-					/* LDO1_OUT --> VDD_SD_DV_REG  */
-					regulator-name = "ldo1";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <3300000>;
-					regulator-always-on;
-					regulator-boot-on;
-					regulator-allow-bypass;
-					u-boot,dm-spl;
-				};
-
-				ldo2_reg: ldo2 {
-					/* VDA_USB_3V3_REG */
-					regulator-name = "ldo2";
-					regulator-min-microvolt = <3300000>;
-					regulator-max-microvolt = <3300000>;
-					regulator-allow-bypass;
-					u-boot,dm-spl;
-				};
-
-				ldo3_reg: ldo3 {
-					/* VDA_PLL_1V8_REG */
-					regulator-name = "ldo3";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-					regulator-boot-on;
-					regulator-always-on;
-					u-boot,dm-spl;
-				};
-
-				ldo4_reg: ldo4 {
-					/* V917_LDO4_1V8 */
-					regulator-name = "ldo4";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-					regulator-boot-on;
-					u-boot,dm-spl;
-				};
-
-				ldo5_reg: ldo5 {
-					/* VPP_EFUSE_1V8 */
-					regulator-name = "ldo5";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-					regulator-always-on;
-					regulator-boot-on;
-					u-boot,dm-spl;
-				};
-			};
-		};
-	};
-};
-
-&wkup_vtm0 {
-	vdd-supply-2 = <&buck12_reg>;
-	som1-supply-2 = <&smps12_reg>;
-	u-boot,dm-spl;
-};
+// &wkup_i2c0 {
+// 	u-boot,dm-spl;
+// 	tps659413a: tps659413a@48 {
+// 		reg = <0x48>;
+// 		compatible = "ti,tps659413";
+// 		u-boot,dm-spl;
+// 		pinctrl-names = "default";
+// 		pinctrl-0 = <&wkup_i2c0_pins_default>;
+// 		clock-frequency = <400000>;
+
+// 		regulators: regulators {
+// 			u-boot,dm-spl;
+// 			buck12_reg: buck12 {
+// 				/*VDD_MPU*/
+// 				regulator-name = "buck12";
+// 				regulator-min-microvolt = <800000>;
+// 				regulator-max-microvolt = <1250000>;
+// 				regulator-always-on;
+// 				regulator-boot-on;
+// 				u-boot,dm-spl;
+// 			};
+// 		};
+// 	};
+
+// 	tps65917: tps65917@58 {
+// 		reg = <0x58>;
+// 		compatible = "ti,tps65917";
+// 		interrupt-controller;
+// 		#interrupt-cells = <2>;
+// 		u-boot,dm-spl;
+
+// 		ti,system-power-controller;
+
+// 		tps65917_pmic {
+// 			compatible = "ti,tps65917-pmic";
+// 			u-boot,dm-spl;
+
+// 			tps65917_regulators: regulators {
+// 				u-boot,dm-spl;
+// 				smps12_reg: smps12 {
+// 					/* VDD_CPU_AVS_REG */
+// 					regulator-name = "smps1";
+// 					regulator-min-microvolt = <800000>;
+// 					regulator-max-microvolt = <1250000>;
+// 					regulator-always-on;
+// 					regulator-boot-on;
+// 					u-boot,dm-spl;
+// 				};
+
+// 				smps3_reg: smps3 {
+// 					/* V917_SMPS3_1V1 */
+// 					regulator-name = "smps3";
+// 					regulator-min-microvolt = <1100000>;
+// 					regulator-max-microvolt = <1100000>;
+// 					regulator-boot-on;
+// 					regulator-always-on;
+// 					u-boot,dm-spl;
+// 				};
+
+// 				smps4_reg: smps4 {
+// 					/* VDD_CORE_RAM_0V85_REG */
+// 					regulator-name = "smps4";
+// 					regulator-min-microvolt = <850000>;
+// 					regulator-max-microvolt = <850000>;
+// 					regulator-always-on;
+// 					regulator-boot-on;
+// 					u-boot,dm-spl;
+// 				};
+
+// 				smps5_reg: smps5 {
+// 					/* VDD_CPU_RAM_0V85_REG */
+// 					regulator-name = "smps5";
+// 					regulator-min-microvolt = <850000>;
+// 					regulator-max-microvolt = <850000>;
+// 					regulator-boot-on;
+// 					regulator-always-on;
+// 					u-boot,dm-spl;
+// 				};
+
+// 				ldo1_reg: ldo1 {
+// 					/* LDO1_OUT --> VDD_SD_DV_REG  */
+// 					regulator-name = "ldo1";
+// 					regulator-min-microvolt = <1800000>;
+// 					regulator-max-microvolt = <3300000>;
+// 					regulator-always-on;
+// 					regulator-boot-on;
+// 					regulator-allow-bypass;
+// 					u-boot,dm-spl;
+// 				};
+
+// 				ldo2_reg: ldo2 {
+// 					/* VDA_USB_3V3_REG */
+// 					regulator-name = "ldo2";
+// 					regulator-min-microvolt = <3300000>;
+// 					regulator-max-microvolt = <3300000>;
+// 					regulator-allow-bypass;
+// 					u-boot,dm-spl;
+// 				};
+
+// 				ldo3_reg: ldo3 {
+// 					/* VDA_PLL_1V8_REG */
+// 					regulator-name = "ldo3";
+// 					regulator-min-microvolt = <1800000>;
+// 					regulator-max-microvolt = <1800000>;
+// 					regulator-boot-on;
+// 					regulator-always-on;
+// 					u-boot,dm-spl;
+// 				};
+
+// 				ldo4_reg: ldo4 {
+// 					/* V917_LDO4_1V8 */
+// 					regulator-name = "ldo4";
+// 					regulator-min-microvolt = <1800000>;
+// 					regulator-max-microvolt = <1800000>;
+// 					regulator-boot-on;
+// 					u-boot,dm-spl;
+// 				};
+
+// 				ldo5_reg: ldo5 {
+// 					/* VPP_EFUSE_1V8 */
+// 					regulator-name = "ldo5";
+// 					regulator-min-microvolt = <1800000>;
+// 					regulator-max-microvolt = <1800000>;
+// 					regulator-always-on;
+// 					regulator-boot-on;
+// 					u-boot,dm-spl;
+// 				};
+// 			};
+// 		};
+// 	};
+// };
+
+// &wkup_vtm0 {
+// 	vdd-supply-2 = <&buck12_reg>;
+// 	som1-supply-2 = <&smps12_reg>;
+// 	u-boot,dm-spl;
+// };
 
 
 &main_r5fss0 {
@@ -477,36 +477,36 @@
 	u-boot,dm-spl;
 };
 
-&usbss0 {
-	/delete-property/ power-domains;
-	/delete-property/ assigned-clocks;
-	/delete-property/ assigned-clock-parents;
-	clocks = <&clk_19_2mhz>;
-	clock-names = "usb2_refclk";
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_usbss0_pins_default>;
-	ti,vbus-divider;
-};
-
-&main_i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_i2c0_pins_default>;
-	clock-frequency = <400000>;
-
-	exp1: gpio@20 {
-		compatible = "ti,tca6416";
-		reg = <0x20>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
-
-	exp2: gpio@22 {
-		compatible = "ti,tca6424";
-		reg = <0x22>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
-};
+// &usbss0 {
+// 	/delete-property/ power-domains;
+// 	/delete-property/ assigned-clocks;
+// 	/delete-property/ assigned-clock-parents;
+// 	clocks = <&clk_19_2mhz>;
+// 	clock-names = "usb2_refclk";
+// 	pinctrl-names = "default";
+// 	pinctrl-0 = <&main_usbss0_pins_default>;
+// 	ti,vbus-divider;
+// };
+
+// &main_i2c0 {
+// 	pinctrl-names = "default";
+// 	pinctrl-0 = <&main_i2c0_pins_default>;
+// 	clock-frequency = <400000>;
+
+// 	exp1: gpio@20 {
+// 		compatible = "ti,tca6416";
+// 		reg = <0x20>;
+// 		gpio-controller;
+// 		#gpio-cells = <2>;
+// 	};
+
+// 	exp2: gpio@22 {
+// 		compatible = "ti,tca6424";
+// 		reg = <0x22>;
+// 		gpio-controller;
+// 		#gpio-cells = <2>;
+// 	};
+// };
 
 &ospi0 {
 	pinctrl-names = "default";
@@ -537,29 +537,29 @@
 	};
 };
 
-&ospi1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
-	u-boot,dm-spl;
-
-	reg = <0x0 0x47050000 0x0 0x100>,
-	      <0x0 0x58000000 0x0 0x8000000>;
-
-	flash@0{
-		compatible = "jedec,spi-nor";
-		reg = <0x0>;
-		spi-tx-bus-width = <1>;
-		spi-rx-bus-width = <4>;
-		spi-max-frequency = <40000000>;
-		cdns,tshsl-ns = <60>;
-		cdns,tsd2d-ns = <60>;
-		cdns,tchsh-ns = <60>;
-		cdns,tslch-ns = <60>;
-		cdns,read-delay = <2>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		u-boot,dm-spl;
-	};
-};
+// &ospi1 {
+// 	pinctrl-names = "default";
+// 	pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
+// 	u-boot,dm-spl;
+
+// 	reg = <0x0 0x47050000 0x0 0x100>,
+// 	      <0x0 0x58000000 0x0 0x8000000>;
+
+// 	flash@0{
+// 		compatible = "jedec,spi-nor";
+// 		reg = <0x0>;
+// 		spi-tx-bus-width = <1>;
+// 		spi-rx-bus-width = <4>;
+// 		spi-max-frequency = <40000000>;
+// 		cdns,tshsl-ns = <60>;
+// 		cdns,tsd2d-ns = <60>;
+// 		cdns,tchsh-ns = <60>;
+// 		cdns,tslch-ns = <60>;
+// 		cdns,read-delay = <2>;
+// 		#address-cells = <1>;
+// 		#size-cells = <1>;
+// 		u-boot,dm-spl;
+// 	};
+// };
 
 #include "k3-j721e-common-proc-board-u-boot.dtsi"
diff --git a/board-support/u-boot-2020.01+gitAUTOINC+3c9ebdb87d-g3c9ebdb87d/arch/arm/dts/k3-j721e-som-p0.dtsi b/board-support/u-boot-2020.01+gitAUTOINC+3c9ebdb87d-g3c9ebdb87d/arch/arm/dts/k3-j721e-som-p0.dtsi
index e143c7b5b..38e5be698 100644
--- a/board-support/u-boot-2020.01+gitAUTOINC+3c9ebdb87d-g3c9ebdb87d/arch/arm/dts/k3-j721e-som-p0.dtsi
+++ b/board-support/u-boot-2020.01+gitAUTOINC+3c9ebdb87d-g3c9ebdb87d/arch/arm/dts/k3-j721e-som-p0.dtsi
@@ -65,18 +65,18 @@
 	};
 };
 
-&hbmc {
-	status = "disabled";
-	pinctrl-names = "default";
-	pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
-	ranges = <0x0 0x0 0x5 0x0 0x4000000>, /* 64MB Flash on CS0 */
-		 <0x1 0x0 0x5 0x4000000 0x800000>; /* 8MB RAM on CS1 */
+// &hbmc {
+// 	status = "disabled";
+// 	pinctrl-names = "default";
+// 	pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
+// 	ranges = <0x0 0x0 0x5 0x0 0x4000000>, /* 64MB Flash on CS0 */
+// 		 <0x1 0x0 0x5 0x4000000 0x800000>; /* 8MB RAM on CS1 */
 
-	flash@0,0 {
-		compatible = "cypress,hyperflash", "cfi-flash";
-		reg = <0x0 0x0 0x4000000>;
-	};
-};
+// 	flash@0,0 {
+// 		compatible = "cypress,hyperflash", "cfi-flash";
+// 		reg = <0x0 0x0 0x4000000>;
+// 	};
+// };
 
 &ospi0 {
 	pinctrl-names = "default";
@@ -87,12 +87,12 @@
 		reg = <0x0>;
 		spi-tx-bus-width = <8>;
 		spi-rx-bus-width = <8>;
-		spi-max-frequency = <25000000>;
+		spi-max-frequency = <50000000>;
 		cdns,tshsl-ns = <60>;
 		cdns,tsd2d-ns = <60>;
 		cdns,tchsh-ns = <60>;
 		cdns,tslch-ns = <60>;
-		cdns,read-delay = <0>;
+		cdns,read-delay = <2>;
 		cdns,phy-mode;
 		#address-cells = <1>;
 		#size-cells = <1>;
diff --git a/board-support/u-boot-2020.01+gitAUTOINC+3c9ebdb87d-g3c9ebdb87d/arch/arm/dts/k3-j721e-tps65917-proc-board.dts b/board-support/u-boot-2020.01+gitAUTOINC+3c9ebdb87d-g3c9ebdb87d/arch/arm/dts/k3-j721e-tps65917-proc-board.dts
index 525e75982..e568e4e7b 100644
--- a/board-support/u-boot-2020.01+gitAUTOINC+3c9ebdb87d-g3c9ebdb87d/arch/arm/dts/k3-j721e-tps65917-proc-board.dts
+++ b/board-support/u-boot-2020.01+gitAUTOINC+3c9ebdb87d-g3c9ebdb87d/arch/arm/dts/k3-j721e-tps65917-proc-board.dts
@@ -1,128 +1,128 @@
 #include "k3-j721e-common-proc-board.dts"
 #include "k3-j721e-common-proc-board-u-boot.dtsi"
 
-&wkup_i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&wkup_i2c0_pins_default>;
-	clock-frequency = <400000>;
-	u-boot,dm-spl;
-
-	tps65917: tps65917@58 {
-		reg = <0x58>;
-		compatible = "ti,tps65917";
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		u-boot,dm-spl;
-
-		ti,system-power-controller;
-
-		tps65917_pmic {
-			compatible = "ti,tps65917-pmic";
-			u-boot,dm-spl;
-
-			tps65917_regulators: regulators {
-				u-boot,dm-spl;
-				smps12_reg: smps12 {
-					/* VDD_CPU_AVS_REG */
-					regulator-name = "smps1";
-					regulator-min-microvolt = <800000>;
-					regulator-max-microvolt = <1250000>;
-					regulator-always-on;
-					regulator-boot-on;
-					u-boot,dm-spl;
-				};
-
-				smps3_reg: smps3 {
-					/* V917_SMPS3_1V1 */
-					regulator-name = "smps3";
-					regulator-min-microvolt = <1100000>;
-					regulator-max-microvolt = <1100000>;
-					regulator-boot-on;
-					regulator-always-on;
-					u-boot,dm-spl;
-				};
-
-				smps4_reg: smps4 {
-					/* VDD_CORE_RAM_0V85_REG */
-					regulator-name = "smps4";
-					regulator-min-microvolt = <850000>;
-					regulator-max-microvolt = <850000>;
-					regulator-always-on;
-					regulator-boot-on;
-					u-boot,dm-spl;
-				};
-
-				smps5_reg: smps5 {
-					/* VDD_CPU_RAM_0V85_REG */
-					regulator-name = "smps5";
-					regulator-min-microvolt = <850000>;
-					regulator-max-microvolt = <850000>;
-					regulator-boot-on;
-					regulator-always-on;
-					u-boot,dm-spl;
-				};
-
-				ldo1_reg: ldo1 {
-					/* LDO1_OUT --> VDD_SD_DV_REG  */
-					regulator-name = "ldo1";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <3300000>;
-					regulator-always-on;
-					regulator-boot-on;
-					regulator-allow-bypass;
-					u-boot,dm-spl;
-				};
-
-				ldo2_reg: ldo2 {
-					/* VDA_USB_3V3_REG */
-					regulator-name = "ldo2";
-					regulator-min-microvolt = <3300000>;
-					regulator-max-microvolt = <3300000>;
-					regulator-allow-bypass;
-					u-boot,dm-spl;
-				};
-
-				ldo3_reg: ldo3 {
-					/* VDA_PLL_1V8_REG */
-					regulator-name = "ldo3";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-					regulator-boot-on;
-					regulator-always-on;
-					u-boot,dm-spl;
-				};
-
-				ldo4_reg: ldo4 {
-					/* V917_LDO4_1V8 */
-					regulator-name = "ldo4";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-					regulator-boot-on;
-					u-boot,dm-spl;
-				};
-
-				ldo5_reg: ldo5 {
-					/* VPP_EFUSE_1V8 */
-					regulator-name = "ldo5";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-					regulator-always-on;
-					regulator-boot-on;
-					u-boot,dm-spl;
-				};
-			};
-		};
-	};
-};
-
-&main_sdhci1 {
-	vqmmc-supply = <&ldo1_reg>;
-};
-
-&usbss0 {
-	/delete-property/ ti,usb2-only;
-};
-
-&usb0 {
-	 dr_mode = "host";
-};
+// &wkup_i2c0 {
+// 	pinctrl-names = "default";
+// 	pinctrl-0 = <&wkup_i2c0_pins_default>;
+// 	clock-frequency = <400000>;
+// 	u-boot,dm-spl;
+
+// 	tps65917: tps65917@58 {
+// 		reg = <0x58>;
+// 		compatible = "ti,tps65917";
+// 		interrupt-controller;
+// 		#interrupt-cells = <2>;
+// 		u-boot,dm-spl;
+
+// 		ti,system-power-controller;
+
+// 		tps65917_pmic {
+// 			compatible = "ti,tps65917-pmic";
+// 			u-boot,dm-spl;
+
+// 			tps65917_regulators: regulators {
+// 				u-boot,dm-spl;
+// 				smps12_reg: smps12 {
+// 					/* VDD_CPU_AVS_REG */
+// 					regulator-name = "smps1";
+// 					regulator-min-microvolt = <800000>;
+// 					regulator-max-microvolt = <1250000>;
+// 					regulator-always-on;
+// 					regulator-boot-on;
+// 					u-boot,dm-spl;
+// 				};
+
+// 				smps3_reg: smps3 {
+// 					/* V917_SMPS3_1V1 */
+// 					regulator-name = "smps3";
+// 					regulator-min-microvolt = <1100000>;
+// 					regulator-max-microvolt = <1100000>;
+// 					regulator-boot-on;
+// 					regulator-always-on;
+// 					u-boot,dm-spl;
+// 				};
+
+// 				smps4_reg: smps4 {
+// 					/* VDD_CORE_RAM_0V85_REG */
+// 					regulator-name = "smps4";
+// 					regulator-min-microvolt = <850000>;
+// 					regulator-max-microvolt = <850000>;
+// 					regulator-always-on;
+// 					regulator-boot-on;
+// 					u-boot,dm-spl;
+// 				};
+
+// 				smps5_reg: smps5 {
+// 					/* VDD_CPU_RAM_0V85_REG */
+// 					regulator-name = "smps5";
+// 					regulator-min-microvolt = <850000>;
+// 					regulator-max-microvolt = <850000>;
+// 					regulator-boot-on;
+// 					regulator-always-on;
+// 					u-boot,dm-spl;
+// 				};
+
+// 				ldo1_reg: ldo1 {
+// 					/* LDO1_OUT --> VDD_SD_DV_REG  */
+// 					regulator-name = "ldo1";
+// 					regulator-min-microvolt = <1800000>;
+// 					regulator-max-microvolt = <3300000>;
+// 					regulator-always-on;
+// 					regulator-boot-on;
+// 					regulator-allow-bypass;
+// 					u-boot,dm-spl;
+// 				};
+
+// 				ldo2_reg: ldo2 {
+// 					/* VDA_USB_3V3_REG */
+// 					regulator-name = "ldo2";
+// 					regulator-min-microvolt = <3300000>;
+// 					regulator-max-microvolt = <3300000>;
+// 					regulator-allow-bypass;
+// 					u-boot,dm-spl;
+// 				};
+
+// 				ldo3_reg: ldo3 {
+// 					/* VDA_PLL_1V8_REG */
+// 					regulator-name = "ldo3";
+// 					regulator-min-microvolt = <1800000>;
+// 					regulator-max-microvolt = <1800000>;
+// 					regulator-boot-on;
+// 					regulator-always-on;
+// 					u-boot,dm-spl;
+// 				};
+
+// 				ldo4_reg: ldo4 {
+// 					/* V917_LDO4_1V8 */
+// 					regulator-name = "ldo4";
+// 					regulator-min-microvolt = <1800000>;
+// 					regulator-max-microvolt = <1800000>;
+// 					regulator-boot-on;
+// 					u-boot,dm-spl;
+// 				};
+
+// 				ldo5_reg: ldo5 {
+// 					/* VPP_EFUSE_1V8 */
+// 					regulator-name = "ldo5";
+// 					regulator-min-microvolt = <1800000>;
+// 					regulator-max-microvolt = <1800000>;
+// 					regulator-always-on;
+// 					regulator-boot-on;
+// 					u-boot,dm-spl;
+// 				};
+// 			};
+// 		};
+// 	};
+// };
+
+// &main_sdhci1 {
+// 	vqmmc-supply = <&ldo1_reg>;
+// };
+
+// &usbss0 {
+// 	/delete-property/ ti,usb2-only;
+// };
+
+// &usb0 {
+// 	 dr_mode = "host";
+// };
diff --git a/board-support/u-boot-2020.01+gitAUTOINC+3c9ebdb87d-g3c9ebdb87d/arch/arm/dts/k3-j721e.dtsi b/board-support/u-boot-2020.01+gitAUTOINC+3c9ebdb87d-g3c9ebdb87d/arch/arm/dts/k3-j721e.dtsi
index b2670752d..de7a5f283 100644
--- a/board-support/u-boot-2020.01+gitAUTOINC+3c9ebdb87d-g3c9ebdb87d/arch/arm/dts/k3-j721e.dtsi
+++ b/board-support/u-boot-2020.01+gitAUTOINC+3c9ebdb87d-g3c9ebdb87d/arch/arm/dts/k3-j721e.dtsi
@@ -18,30 +18,30 @@
 	#size-cells = <2>;
 
 	aliases {
-		serial0 = &wkup_uart0;
-		serial1 = &mcu_uart0;
+		// serial0 = &wkup_uart0;
+		// serial1 = &mcu_uart0;
 		serial2 = &main_uart0;
-		serial3 = &main_uart1;
-		serial4 = &main_uart2;
-		serial5 = &main_uart3;
-		serial6 = &main_uart4;
-		serial7 = &main_uart5;
-		serial8 = &main_uart6;
-		serial9 = &main_uart7;
-		serial10 = &main_uart8;
-		serial11 = &main_uart9;
-		i2c0 = &wkup_i2c0;
-		i2c1 = &mcu_i2c0;
-		i2c2 = &mcu_i2c1;
-		i2c3 = &main_i2c0;
-		i2c4 = &main_i2c1;
-		i2c5 = &main_i2c2;
-		i2c6 = &main_i2c3;
-		i2c7 = &main_i2c4;
-		i2c8 = &main_i2c5;
-		i2c9 = &main_i2c6;
+		// serial3 = &main_uart1;
+		// serial4 = &main_uart2;
+		// serial5 = &main_uart3;
+		// serial6 = &main_uart4;
+		// serial7 = &main_uart5;
+		// serial8 = &main_uart6;
+		// serial9 = &main_uart7;
+		// serial10 = &main_uart8;
+		// serial11 = &main_uart9;
+		// i2c0 = &wkup_i2c0;
+		// i2c1 = &mcu_i2c0;
+		// i2c2 = &mcu_i2c1;
+		// i2c3 = &main_i2c0;
+		// i2c4 = &main_i2c1;
+		// i2c5 = &main_i2c2;
+		// i2c6 = &main_i2c3;
+		// i2c7 = &main_i2c4;
+		// i2c8 = &main_i2c5;
+		// i2c9 = &main_i2c6;
 		spi0 = &ospi0;
-		spi1 = &ospi1;
+		// spi1 = &ospi1;
 	};
 
 	chosen { };

Thanks

Hi Jianyu huo,

With some modification to the DT and by using eMMC for File System and skipping u-boot from the boot flow. I am able to get to linux in ~11sec. With limited validation I can say vision_apps is functional. (ran app_tidl demo).

Logs: (match global time stamps to get timing)

SBL Revision: 01.00.10.00 (May 11 2021 - 15:57:27)
[2021-05-13 04:30:26.819] TIFS  ver: 21.1.1--v2021.01a (Terrific Lla

main_uart.log

I will keep you posted on further development here.

Regards,

Karan

Hi Karan，

We are also working on skipping u-boot. Waiting for your good news.

Hi Jianyu huo,

The ~11s boot time I got was by skipping u-boot. I can send you patches on how to do that later today.

Regards,

Karan

Hi Jianyu huo,

Not sure if you were able to get the combined optimized image from SBL (without u-boot). So sending patches. This will let you boot to prompt in ~11sec.

Patch on Linux: https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/0001_2D00_baidu_2D00_fast_2D00_boot.patch

Patch on PDK: https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/0001_2D00_combined_2D00_image_2D00_opt_2D00_Add_2D00_vision_5F00_apps_2D00_FWs_2D00_and_2D00_Linux_2D00_DTB.patch

Logs as attached in this response: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/995417/tda4vm-how-to-optimize-boot-time-on-a72/3698226#3698226

Regards,

Karan

Hi Karan,

Thank you for your updates, we will try your patch soon. 11s is a big step forward but there is still a long way to go.

I think you will do further optimizations on communications between A72 and other cores, right?

Thanks.

Hi Jianyu Hua,

11s was with still a lot of non essential DT nodes still in. We can knock them off and then look at reduction of some prints from Kernel. That should save us some time again. Will keep you posted, let me know when you are able to consume these patches and are at the same baseline as me.

Regards,

Karan

Hi Jianyu Huo,

Yes we are continuing to optimize the time. We are around 8.8S right now. Further optimizations will take more time.
In the mean time can you feedback on the 11S patches? Are you able to get to what we are seeing?

Karan will be sharing a patch to further reduce to 8.8 Seconds.

Best Regards,
Keerthy

Hi Jianyu Huo,

Please use that patches attached here to get to 8.8s to Linux prompt.

Also, do confirm when you are able to replicate these numbers on your side. These are with OSPI (boot) + eMMC (filesystem).

Patches:

Linux:

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/6607.0001_2D00_baidu_2D00_fast_2D00_boot.patch

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/0002_2D00_Make_2D00_loglevel_2D00_0_2D00_in_2D00_bootargs.patch

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/0003_2D00_Trim_2D00_DT_2D00_further.patch

PDK:

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/0842.0001_2D00_combined_2D00_image_2D00_opt_2D00_Add_2D00_vision_5F00_apps_2D00_FWs_2D00_and_2D00_Linux_2D00_DTB.patch

The commit messages are self explanatory, but let me know if you want more details.

Regards,

Karan

Hi Karan Saxena ,

I have a questions about your PDK patch: 0001-combined-image-opt-Add-vision_apps-FWs-and-Linux-DTB.patch

To test  your patch, we should use "combined image" (sbl+app fws+atf+kernel+dtb)  ? How to get it?

Hi, Wenguang Qui,

You can follow the section "Using the combined_appimage tooling to boot a HLOS+RTOS appimage" in https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/07_03_00_07/exports/docs/pdk_jacinto_07_03_00_29/docs/userguide/jacinto/boot/boot_k3.html 

Essentially how you were building the combined app with SPL, you need to apply the patch I send and then do the same.

Regards,

Karan

Hi, Karan Saxena,

According to the guide you mentioned, I got a build error:

================================

qiuwenguang@sixi:~/Projects/baidu/acu/sixi_sdk/ti/ti-processor-sdk-rtos-j721e-evm-07_02_00_06/pdk_jacinto_07_01_05_14/packages/ti/boot/sbl/tools/combined_appimage$ make BOARD=j721e_evm GCC_LINUX_ARM_PATH=/home/qiuwenguang/Projects/baidu/acu/sixi_sdk/ti/ti-processor-sdk-rtos-j721e-evm-07_02_00_06/gcc-arm-9.2-2019.12-x86_64-aarch64-none-elf

make: *** No rule to make target '/home/qiuwenguang/Projects/baidu/acu/sixi_sdk/ti/ti-processor-sdk-rtos-j721e-evm-07_02_00_06/pdk_jacinto_07_01_05_14/packages/ti/binary/ipc_echo_testb/bin/j721e_evm/ipc_echo_testb_mcu1_0_release_strip.rprc', needed by '/home/qiuwenguang/Projects/baidu/acu/sixi_sdk/ti/ti-processor-sdk-rtos-j721e-evm-07_02_00_06/pdk_jacinto_07_01_05_14/packages/ti/boot/sbl/tools/combined_appimage/bin/j721e_evm/combined.appimage'. Stop.

================================

The combined appimage is built from a number of RPRC files,  but I can not find them.

Thank you.

Hi Keerthy,

11s version is still under developing. My colleague Wenguang Qiu is working on it.

Is there any updates on how to reduce communications between A72 and other cores, or is it feasible？

I think that is more important, since we also have the ability to do some general optimization on linux, but communication optimization strongly relys on TI.

So please give us more details about that if possible.

Thanks.

Hi Wenguang,

You have probably not built the SDK before running this command. You need to have the vision_apps and the pdk built before you run compile the combine image.

Can you please take a look at the vision_apps user guide here https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/07_03_00_07/exports/docs/vision_apps/docs/user_guide/BUILD_INSTRUCTIONS.html to build the SDK?

Regards,

Karan

Hi Karan Saxena，

Actually，before running the command(compile combined image), I already had vision_apps and pdk built. but I still got the build error(no rprc files)

you can check our build script.

=======================

=======================

Thank you.

Hi Wenguang,

Wenguang Qiu said:

The combined appimage is built from a number of RPRC files,  but I can not find them.

The rprc files are not there in the SDK by default when you build the app. As a part of the combined image generation, the rprc files are generated by using the out2rprc utility. See makefile in the combined_appimage directory.

Regards,

Karan

Hi,

Wenguang Qiu said:

make: *** No rule to make target '/home/qiuwenguang/Projects/baidu/acu/sixi_sdk/ti/ti-processor-sdk-rtos-j721e-evm-07_02_00_06/pdk_jacinto_07_01_05_14/packages/ti/binary/ipc_echo_testb/bin/j721e_evm/ipc_echo_testb_mcu1_0_release_strip.rprc', needed by '/home/qiuwenguang/Projects/baidu/acu/sixi_sdk/ti/ti-processor-sdk-rtos-j721e-evm-07_02_00_06/pdk_jacinto_07_01_05_14/packages/ti/boot/sbl/tools/combined_appimage/bin/j721e_evm/combined.appimage'. Stop.

Do you have /home/qiuwenguang/Projects/baidu/acu/sixi_sdk/ti/ti-processor-sdk-rtos-j721e-evm-07_02_00_06/pdk_jacinto_07_01_05_14/packages/ti/binary/ipc_echo_testb/bin/j721e_evm/ipc_echo_testb_mcu1_0_release.xer5f file? This would be needed to create the .rprc.

Regards,

Karan

Hi Karan Saxena,

After I modified the "IMG" path in config.mk, I can get "combined.appimage".

How to flash it onto OSPI device?

Thank you.

Hi Wenguang,

You need to flash the:

sbl_ospi_img_hlos_mcu1_0_release.tiimage at 0x0.

tifs.bin at 0x80000

combined.appimage at 0x100000

You can use UNIFLASH to flash to the OSPI flash or I would recommend use u-boot to flash which will be much faster.

jianyu huo said:

Time is measured with OSPI boot, SBL/SPL/U-Boot are in OSPI Flash and kernel is in eMMC. For your question,

You can also probably do the same way Jianyu Hua did as he has done this flashing to OSPI when reporting the baseline number.

Regards,

Karan

Hi, Karan,

   I take over this case now and I'm studying the history and documentation of this case. 

   I will try your solution about "11sec " , The size of combined.appimage  is 100M and our ospi size is 32M. 

   Could we boot the system with : 

   sbl_ospi_img_hlos_mcu1_0_release.tiimage(ospi) -> tifs.bin(ospi) -> combined.appimage(emmc) ?

Hi,

The image which I built was 31MB. Are you using the latest set of patches?

other wang said:

   Could we boot the system with : 

   sbl_ospi_img_hlos_mcu1_0_release.tiimage(ospi) -> tifs.bin(ospi) -> combined.appimage(emmc) ?

This would be a custom implementation not supported by the SBL combined image boot you are trying without u-boot.

Without u-boot, all the remote core firmwares are now a part of the combined.appimage and are loaded by SBL. That is why the image is larger.

The SBL will only initialize the boot media, the boot media will be the media from where the ROM code has picked up the SBL from. This in the this case is OSPI. So eMMC will not be initialized by default from SBL.

Lets first see why the image you are building is larger than expected and then look for alternatives if needed.

Regards,

Karan

Hi, 

   You are right,  according  to the config.mk at ti-processor-sdk-rtos-j721e-evm-07_02_00_06/pdk_jacinto_07_01_05_14/packages/ti/boot/sbl/tools/combined_appimage ,  

 IMG_LIST ?= $(IMG1) $(IMG2) $(IMG3) $(IMG4) $(IMG5) $(IMG6) $(IMG7) $(IMG8) $(HLOS_IMGS)

136 #IMG1 ?= mcu1_0,$(SDK_INSTALL_PATH)/targetfs/lib/firmware/pdk-ipc/ipc_echo_testb_mcu1_0_release_strip.xer5f
137 #IMG2 ?= mcu2_0,$(VISION_APPS_FW_PATH)/R5F/SYSBIOS/release/vx_app_tirtos_linux_mcu2_0.out
138 #IMG3 ?= mcu2_1,$(VISION_APPS_FW_PATH)/R5F/SYSBIOS/release/vx_app_tirtos_linux_mcu2_1.out
139 #IMG4 ?= c66xdsp_1,$(VISION_APPS_FW_PATH)/C66/SYSBIOS/release/vx_app_tirtos_linux_c6x_1.out
140 #IMG5 ?= c66xdsp_2,$(VISION_APPS_FW_PATH)/C66/SYSBIOS/release/vx_app_tirtos_linux_c6x_2.out
141 #IMG6 ?= c7x_1,$(VISION_APPS_FW_PATH)/C71/SYSBIOS/release/vx_app_tirtos_linux_c7x_1.out

So the combined.appimage is large.  

Without u-boot, all the remote core firmwares are now a part of the combined.appimage and are loaded by SBL. That is why the image is larger.

Is there any way to remove these part?  Since our ospi size is 32M and we need to store another data to the emmc,  so the avaliable size for combined.appimage is about 10M,  is there any solution about it?

Regards

Wang Hongjie

Hi,

So to improve boot time, we removed the u-boot stage from the boot flow.

What is your flash layout? Can you please help me understand that? How is the 32 MB getting use?

Even for a 32 MB flash, the images I build should work, as the tiboot3.bin + tifs.bin + app is slightly less than 32MB. But again, this is on the margin.

Regards,

Karan

The following is our OSPI flash partition table,  in order to support FastBoot, corresponding adjustments should be made ,but the total size is 32G , and we need to support AB partition for OTA , so the avaliable space should be around 10G. 

mtdparts=mtdparts=47040000.spi.0:512k(ospi.sbl),512k(ospi.tifs_a),512k(ospi.tifs_b),4m(ospi.mcufw_a),4m(ospi.mcufw_b),2m(ospi.atf_optee_a),2m(ospi.atf_optee_b),1m(ospi.u-boot-spl_a),1m(ospi.u-boot-spl_b),2m(ospi.u-boot_a),2m(ospi.u-boot_b),128k(ospi.misc_a),128k(ospi.misc_b),128k(ospi.factory),4325376(ospi.reserved),8m(ospi.mcudata)

Now I am tring  your suolution with only one IMG ( only include IMG1 , linux Image and dtbs ) , it is 17M ,   and i will report the result ASAP. 

By the way , since linux boot time should be 4s and the mcu1_0 boot time should be 100ms,  how about the mcu1_0 in your solution?

Hi,

SBL booting linux in the manner we are discussing on this thread, can not give you an early MCU1_0 (<100ms).

As far as I know, your use case was surround view, has that changed?

For an early MCU1_0 app, we need to go via a different route which involves an intermediate application on MCU1_0 which runs some task early (~50ms) and then boots the rest of the cores (including Linux on A72) by acting like a tertiary boot loader. See http://downloads.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/mcusw/mcal_drv/docs/drv_docs/demo_boot_app_mcu_rtos_top.html 

Regards,

Karan

Hi, Karan,

    The kernel boot successfully now,  do you know how to add the parameter of kernel in the combined mode ? 

Hi Wang,

Are you able to run vision_apps from the kernel now?

- Keerthy

Hi Wang,

What do you mean by parameter for kernel in combined mode? Are you looking for a way to pass the kernel boot args?

Regards,

Karan

Hi, Karan,

  About your questions:

  Are you able to run vision_apps from the kernel now?

       No,  since we couldn't  send kernel’s command-line parameters to kernel ,  there isn't rootfs . the kernel is running now and panic without rootfs. 

  Are you looking for a way to pass the kernel boot args?

       Yes,  please  show me how ot pass the  kernel’s command-line parameters to kernel  in combined mode.  build the parameters into kernel is not a good way.

Wang Hongjie

Hi,

Karan Saxena said:

Linux:

6607.0001-baidu-fast-boot.patch

0002-Make-loglevel-0-in-bootargs.patch

0003-Trim-DT-further.patch

In this response from me (https://e2e.ti.com/support/processors-group/processors/f/processors-forum/995417/tda4vm-how-to-optimize-boot-time-on-a72/3710306#3710306 ), I have attached the Linux patches. In the 0001 patch I am passing the bootargs via the chosen node. This is where I specify where the root file system is (root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait). I had changed this to /dev/mmcblk0p2 which is the file system in eMMC. You need to flash the file system in eMMC, have you done that?

Regards,

Karan

Hi,Karan,
Maybe I didn’t clarify my issues, so please allow me to explain again.
linux boot time need to be reduced to 4s, use the "combined.appimage" sulotion which you provided, we can run the kernel now. but there are still some problems not clear.
1. Our ospi flash is 32M , if we compile all fws into a combined file(combined.appimage), the file size will be 100M, according to your answer, the follow files are necessary for the combined mode:
a. sbl_ospi_img_hlos_mcu1_0_release.tiimage
b. tifs.bin
c. combined.appimage
so the question is : Can we put file a&b into ospi and file c into emmc to complete the boot?

2. It is not a good way to compile the kernel boot args into dtb or kernel, it will affect our ota , can we pass kernel startup args to kernel as uboot in combined mode.

3. I find that it takes a long time(about 6s) for A72 to communicate with R5fs and DSPs. how to optimize it or is there any reference design?

Please help us to make them clear, we will consider our design based on your information


Thanks

Hi,

other wang said:

. I find that it takes a long time(about 6s) for A72 to communicate with R5fs and DSPs. how to optimize it or is there any reference design?

This is the limitation of Linux remoteproc driver as it needs to read & load the firmware from resource table in the filesystem.
This will not be straight forward as the driver needs filesystem to be up which takes around 6 seconds to read the resource table
from the firmware. This is by design & i am in touch with the IPC experts. This will be a complicated exercise to bypass the need
to read the firmware from filesystem. So this part will be needing more time to work around.

Best Regards,
Keerthy

Hi, Keerthy and Karan. 

   Thank you very much for your attention , is there any information on questions 1 and 2 ?

   About the work around , can  you estimate the time required for implementation ?

Best Regards,

Wang Hongjie

Hi,

other wang said:

1. Our ospi flash is 32M , if we compile all fws into a combined file(combined.appimage), the file size will be 100M, according to your answer, the follow files are necessary for the combined mode:
a. sbl_ospi_img_hlos_mcu1_0_release.tiimage
b. tifs.bin
c. combined.appimage
so the question is : Can we put file a&b into ospi and file c into emmc to complete the boot?

SBL can only load images from the boot media where it has come up from. So of you are loading SBL from OSPI, it can boot the application only from OSPI hence the combined.appimage with this boot flow can be picked up from OSPI only.

If there was something like A72 SPL and A72 u-boot in the boot flow then there was a liberty of booting firmwares from eMMC and SBL inn that case will only load a small A72 SPL image from OSPI. But this will add to the boot time.

other wang said:

2. It is not a good way to compile the kernel boot args into dtb or kernel, it will affect our ota , can we pass kernel startup args to kernel as uboot in combined mode.

With SBL combined image, you can only pass the boot args via the DTB which is a part of the combined.appimage. You can pass the bootargs via the chosen node in the DTB and then create the combined.appimage with the new DTB.

In the current boot flow you are using, there is no u-boot.

Regards,

Karan

It seems that this limitation of SBL will block the solution, does Ti have any solution to reduce the size of combined.appimage? 

Hi Wang,

The other boot flow is SPL/u-boot based boot flow and if you need the flexibility of u-boot then we can not achieve the timing
we get with SBL as we bypass the uboot altogether with SBL boot flow.

- Keerthy

Hi, Keerthy, 

    Thanks for your comfirmation,   anyway,  we hope to reduce starup time on the whole tda4vm system.

For the combined mode :

     Does Ti support compression of combined.appimage to reduce the size?

For other solution:

     Are there any other suggestions to reduce the startup time?

For optimizing time for A72 communicating with other cores:

    According to your reply, this part will be needing more time to work around, Do you think how to time can finish the workaround?

Regard

WangHongjie

Anyupdate about this issue?

Hi Keerthy, 

Since we are not sure if we can use the combined mode,  we want to optimizate other parts.

I merge your patch and set loglevel=0 ,  the kernel boot time ("Starting kernel"  to "Run /sbin/init as init process") reduced by 2100ms, but the network cannot be used after startup, may be caused by timing changed.  

log attached, please give some advice to fix this problem,  there are boot log and the print of dmesg.

.normal_nodelay_loglevel0_dmesg.log

Regards

WangHongjie

Hi,

Anyupdate about this issue?

I heard that TI have reduced the startup time to 7 seconds, can you provide to us?

Regards.

Wang,

No updates after 8.8S. We are brainstorming internally as communicated over the call. We will keep you
posted on further optimizations planned early next week.

Thanks,
Keerthy

Wang,

I have a question of your OSPI memory size. Will you have 32MB fully available for appImage?
With removal of c7x/c6x firmware we see the combined appImage size is 24MB. Is that okay for you?

- Keerthy

Hi, keerthy,

     I think 24MB is too large ,  I  share  the layout about the ospi flash to   "Han, Tao <tao-han@ti.com>"  by email and ask him to forward it to you.

The following is the size of the firmwares and kernel
[2021-07-08 09:42:02.305] -rwxr--r-- 1 root root 22787812 Apr 19 2021 j7-main-r5f0_0-fw*
[2021-07-08 09:42:02.305] -rwxr--r-- 1 root root 13976760 Apr 19 2021 j7-main-r5f0_1-fw*
[2021-07-08 09:42:11.842] -rwxr-xr-x 1 root root 16797704 Sep 12 21:07 Image*

Regards

Wang,

I want you to be doubly sure on the firmware size.

other wang said:

[2021-07-08 09:42:02.305] -rwxr--r-- 1 root root 22787812 Apr 19 2021 j7-main-r5f0_0-fw*

Is it the stripped version?

Look at the below from vision_apps:
ls -l /home/keerthy/work/ti-processor-sdk-rtos-j721e-evm-07_03_00_07/vision_apps/out/J7/R5F/SYSBIOS/release/vx_app_tirtos_linux_mcu2_0.out

-rw-rw-r-- 1 keerthy keerthy 22971980 Jul  8 23:30 /home/keerthy/work/ti-processor-sdk-rtos-j721e-evm-07_03_00_07/vision_apps/out/J7/R5F/SYSBIOS/release/vx_app_tirtos_linux_mcu2_0.out

But what we load finally is a stripped version:

ls -l /tmp/tivision_apps_targetfs_stage/lib/firmware/vision_apps_evm/vx_app_tirtos_linux_mcu2_0.out

-rw-rw-r-- 1 keerthy keerthy 5265752 Jul  8 23:30 /tmp/tivision_apps_targetfs_stage/lib/firmware/vision_apps_evm/vx_app_tirtos_linux_mcu2_0.out

Only 5MB. Can you confirm the size of the firmware on your system?

Regards,
Keerthy

Hi, 

   The j7-main-r5f0_0-fw is not stripped on our side.  but we can only take out 10M storage in ospi flash at most for the combined binary.

Regards