66AK2G12: EPWM HRCTL REGISTER

Hi Richard,

Can you please let me know below?
1. Are you seeing issue in both ARM core (a15) and DSP core OR one of them? Which CPU core is of your interest?

2. What is the Processor SDK version you are using? Is it Processor SDK 6.3 for K2G EVM?

Please let me know.

Thanks

Hi Aravind,

I'm using only the DSP core with the Processor SDK 6.03. Should I initialize the EPWM with the ARM core? 

Best regards

Hi Richard,

Thanks for the details.

AFAIK, there should not be a need to initialize the EPWM with the ARM core. It should be accessible to DSP for initialization and use.

Can you please try if you are able to write to that register location directly using CCS memory browser window? Want to rule out if there is a bug in CSL_epwmHighResolutionCfg().

Thanks

I'm not able to write directly using CCS memory browser. This was my first try, but I don't know why. I can not write with the CSL_epwmHighResolutionCfg() function, HWWrite16 or the Memory browser. As I can see the CSL_epwmHighResolutionCfg() seems to work correctly.

Thank you very much!

Hi Richard,

I see below in the TRM: You would need to enable EPWM_EALLOW bit to 1 in BOOTCFG_EPWM_CTL register to enable HRPWM config register write access enable as per below.

Can you please try it and let me know if this resolves your issue?

Hi Aravind,

sorry my code was not up to date. I have already tried to set the EALLOW bit. There was no success. Here my actual code:

void PWM_init(){
    /*Time base clock configuring using prescaler*/
    CSL_epwmTbTimebaseClkCfg(CSL_PWM_3_CFG_REGS, TBCLK_FREQ, MODULE_CLK);
    CSL_epwmTbTimebaseClkCfg(CSL_PWM_4_CFG_REGS, TBCLK_FREQ, MODULE_CLK);

    /*Sync 3A and PWM5A*/
//    CSL_epwmTbSyncEnable(CSL_PWM_3_CFG_REGS, 0, CSL_EPWM_TB_CNT_DIR_AFT_SYNC_UP);
    CSL_epwmTbSetSyncOutMode(CSL_PWM_3_CFG_REGS,CSL_EPWM_TB_SYNC_OUT_EVT_CNT_EQ_ZERO);
    CSL_epwmTbSyncEnable(CSL_PWM_4_CFG_REGS, 0, CSL_EPWM_TB_CNT_DIR_AFT_SYNC_UP);

    /*Configuring the EPWM_AQCTLA register*/
    CSL_epwmAqActionOnOutputCfg(CSL_PWM_3_CFG_REGS, CSL_EPWM_OUTPUT_CH_A, &aqctrla);
    CSL_epwmAqActionOnOutputCfg(CSL_PWM_3_CFG_REGS, CSL_EPWM_OUTPUT_CH_B, &aqctrlb);
    CSL_epwmAqActionOnOutputCfg(CSL_PWM_4_CFG_REGS, CSL_EPWM_OUTPUT_CH_A, &aqctrla);

    /*Set frequency*/
    CSL_epwmTbPwmFreqCfg(CSL_PWM_3_CFG_REGS, TBCLK_FREQ, PWM_FREQ2, TB_COUNT_UP, TB_IMMEDIATE);
    CSL_epwmTbPwmFreqCfg(CSL_PWM_4_CFG_REGS, TBCLK_FREQ, PWM_FREQ, TB_COUNT_UP, TB_IMMEDIATE);

    CSL_epwmCounterComparatorCfg(CSL_PWM_3_CFG_REGS, CSL_EPWM_CC_CMP_A, (int)1041, CC_SHADOW, CC_CTR_ZERO, OVER_WRITE_SHADOW_DISABLED);
    CSL_epwmCounterComparatorCfg(CSL_PWM_4_CFG_REGS, CSL_EPWM_CC_CMP_A, (int)260, CC_SHADOW, CC_CTR_ZERO, OVER_WRITE_SHADOW_DISABLED);


//    CSL_epwmHrLoadCmpAHrValue(CSL_PWM_3_CFG_REGS,1,CSL_EPWM_HR_REG_ACT_LOAD_CNT_ZRO_PULSE);
    /*Set SOCA for EDMA PWM */
    HW_WR_REG16(0x021D0C32,0x900);
    HW_WR_REG16(0x021D0C34,0x500);

    //Set EALLOW
    HW_WR_REG32((CSL_BOOT_CFG_REGS + BOOTCFG_EPWM_CTL_REG_OFFSET), 0x10038);
    //SETUP EPWM DELMODE to falling edge
    HW_WR_REG16(0x021D0C40,0x0);
    HW_WR_REG16(0x021D0C40,0x2);
    //Clear EALLOW
    HW_WR_REG32((CSL_BOOT_CFG_REGS + BOOTCFG_EPWM_CTL_REG_OFFSET), 0x38);


//    CSL_epwmHighResolutionCfg(CSL_PWM_3_CFG_REGS,CSL_EPWM_HR_DELAY_BUS_SEL_CMPAHR, CSL_EPWM_HR_DELAY_EDGE_CTRL_FALLING);


}

I'm a little bit confused. In the TRM later, there is no protection of the HRPWM CONFIG register. Nevertheless I have already tried it. 

Thanks you!

It is possible that you can reproduce this to get a solution?

Hi Richard,

Sure.. Can you please share your CCS test project?

Thanks

There is only the HRPWM inside with initialisation. If you need more please say it.

Thank you very much!!!

The Outputs are PWM3A&B and synced PWM4 with 384 kHz. Do you need the GEL file as well? My DSP is overclocked to 1200 MHz. With the standard GEL-file it is 80 kHz and 320 kHz.

l8032.K2G.zip

Hi Richard,

Thanks for sharing the project. I will take a look on this during this week and get back to you.

Thanks

Thank you very much!

You are genius. Saved my day! Many thanks!

Naturally, I could not test all yesterday. I still can not write into Register HRCTL of ePWM3. I noticed that the EPWM CTL register is not protected in the latest SDK 6.03 version. 

Would it possible to check? 

Many thanks.

Hi Richard,

Sorry to learn that you are not able to write to HRCTL register. Let me check on this further with few internal team members.

Please expect some delay on this.

Thanks

Thanks!

Hi Aravind,

Is there any progress? I tried to write through PRU. No success.

Thanks 

Richard

Richard,

Sorry!  No update yet from my side. At the moment, this seems to be beyond software apps support. I am checking this with HW Apps team regarding this issue.

Thanks.

Thank you, Aravind. Unfortunately I cannot solve myself the problem.

Hi Richard,

I understand. Sorry it is taking time! At the moment, this is still under investigation/review internally.

Thanks

Hi Aravind,

I tried to write the adress 0x032D0CC0 and it does work! Really nice work! Thank you very much!!! It can be closed.

Best regards to your team, too.

Richard