• State
  • Locked Locked
  • Replies 5 replies
  • Subscribers 100 subscribers
  • Views 468 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SPI port on OMAP-L138 with ENALE

Boris Ruvinsky
Expert 1410 points
Other Parts Discussed in Thread: OMAP-L138

Dear E2E:

Thank you very much for your respond and help.

I have two more question about SPI interface on OMAP-L138.

1.  SPI_CLK is determine by Prescaler value:  SPI_CLK_freq = "SPI module clock"/(PRESCALE+1).

 When (PRESCALE+1) is not "even" value - SPI_CLK is not 50% duty cycle. Is it correct?

I use CLK POLARITY = 0 and I have (PRESCALE+1) = 5. I expect the SPI_CLK duty cycle to be 60% for "CLK high" and 40% for "CLK low".

Is this correct? I could not find it in the data sheet and User Guide.

2.  I use 4-wire interface with Enable. I need to transfer 4x16-bit words without any delays between transfers. Is CSHOLD bit  in register SPIDAT1 applicable in 4-wire mode with ENABLE? ENABLE will stay active (low) for the sufficient time and I will set CSHOLD=1 and WDEL=0 in SPIDAT1 register.

Thank you,

Boris Ruvinsky

  • 0
    TI__Genius 9490 points

    Boris,

    on #1.  I am fairly confident that the SPI Duty cycle is 50% for even/odd Prescale values.  I'm triple checking with module owner to re-confirm :).  I've checked it on the bench and it is 50% in both cases. 

    on #2.  I think what you are describing is the 5-pin mode rather than 4pin mode as explained in the Technical Ref manual http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf (section 30.2.10 SPI Operation: 5-Pin Mode, and inside the CSHOLD bit description in Table 30-21), in which case the CSHOLD Bit is applicable as well only when the SPI is in master mode. 

    BTW lets keep the different questions on separate posts. ( I meant to reply to this one only) and you can close the other one.

    regards,

    miguel

  • 0 in reply to Miguel A. Alanis
    TI__Genius 9490 points

    Boris,

    just to confirm, on #1, SPI clk duty cycle is 50% for even and for odd prescale values. Additionally this is on the device datasheet table 5-70.

    regards,

    miguel

  • 0 in reply to Miguel A. Alanis
    Expert 1410 points

    Hi Miguel.

    Thank you very much for your information.

    It is very important to know this feature of SPI port on OMAP-L138.

    For example McBSP does not have 50% duty cycle with odd divider - that in the UG (SPRUH77) page1166 and in DS Table 5-66 (SPRS586D) - the high state is wider than low state.

    I was sure - the same design was made for SPI. But - thank you - you help to resolve this.

    I am looking into table 5-70 in DS (SPRS586D) - there is no clear statement about 50% duty cycle for SPI0_CLK.

    But there are the parameters tW(SPCH)M = tW(SPCL)M = 0.5M-1 which are explaining that.

    But it would be more clear to add this statement in SPI port documentation - User Guide and DS.

    Can I ask you one more question about SPI port?

    1. As I see in SPIDAT1 Register description - SPIx_CS[n] can stay active (if CSHOLD=1 and WDEL=0) indefinitely "until a control field with new data and control information is loaded into SPIDAT1". That means this time is controlled totally by SW and can be any value. Like 1 hour or 1 day. Is this correct? This is a very good SPI feature.

    Thank you again for your help,

    Boris Ruvinsky

  • 0 in reply to Boris Ruvinsky
    TI__Genius 9490 points

    Boris,

    each peripheral is different, those parameters are good enough to explain that specification else it will be noted there just like the mcbsp is for that parameter, all timing related parameters reside in the device datasheet.

    as for the new question, yes it can be turned off by sw either automatically by changing the control field with new data and control information loaded into SPIDAT1 or manually by turning the CSHOLD bit off :)

    regards,

    miguel

  • 0 in reply to Miguel A. Alanis
    Expert 1410 points

    Hi Miguel.

    Thank you very much for your help.

    Whei am looking on figure 5-40 (SPI timing for 4 wires and 5 wires interface) - I see Master out MO(0) is always valid (on the picture) before SCLK is active and before CS is active.

    Are there any timing parameters for MO(0) valid before  sCLK or CS valid?

    And grey area for the Master data SPI_SIMO - is it "tri-stated" or "not defined".

    Thank you again for your help,

    Boris Ruvinsky