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RTOS/AM5728: Memory mapping for DSP

Thomas N.
Intellectual 475 points
Part Number: AM5728
Other Parts Discussed in Thread: SYSBIOS

Tool/software: TI-RTOS

Hello TI,

Hello Community,

I would like to use both DSPs for two dedicated network stacks. Each one has two main tasks: Task 1 for network stack and task 2 for controlling and stabilizing network clients. To satisfy the scheduling, the DSPs have to use a cache. I am using TI RTOS (version 3.02.00.05) on both DSPs and I would like to configure my memory in a sustainable way to counteract possible amount of changes or variants in the future. After studying the TI corePac manual and browsing the internet, in one off the TI forums (if I recall correctly) I found a solution to enable the (L2) cache with the help of CSL by calling the following functions:

CACHE_enableCaching(128);
...
CACHE_enableCaching(159);
CACHE_setL2Size(CACHE_256KCACHE);
CACHE_wbInvAllL2(CACHE_WAIT);

Thus, I can reduce my cycle time by 33%. That sounds quite good. But I would like to understand these lines and this approach, respectively.

  1. The CACHE_enableCaching(<region>) sets the MAR bits and finally a 16 MB region in DDR3 as cacheable. The argument represents the memory offset, started for example at 0x0_8000_0000. So in my example, I set the following external memory address range (DDR3) as cacheable:
    1. start address: 0x0_8000_0000 + 0x0_7F00_0000 = 0x0_FF00_0000
    2. end address:  0x0_8000_0000 + 0x0_9F00_0000 = 0x1_1F00_0000
    3. size: 0x2000_0000 = 512 MB
      Is this correct?
  2. I am using TI RTOS and I would like to avoid the cache configuration in code. Rather, I would like to do this statically in the configuration and memory file. Is this possible? What is the counterpart for the xdc tools? I tried something like 
    var Cache = xdc.useModule('ti.sysbios.family.c66.Cache');
Cache.setMarMeta(0x80000000, 0x00100000, Cache.PC | Cache.PCX | Cache.PFX | Cache.WTE);
or
Cache.setMarMeta(0x86000000, 0x0600000, 0xD);
     without any success
  3. What is the difference between line 4 (CACHE_setL2Size(CACHE_256KCACHE);) and the command in a .bld-file: l2Mode: "256k"?
  4. What does CACHE_wbInvAllL2(CACHE_WAIT) really do?
  5. What about L1 Cache? How can I configure this?

Is this all possible without creating or modifying the platform described here or here?

Thanks for your help.

Best regards

Thomas

  • 0
    TI__Guru**** 393215 points
    The RTOS team have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    TI__Guru* 95265 points
    Hi,

    1. CACHE_enableCaching(128); ... CACHE_enableCaching(159); Each region used here is 16MB.
    128: means DDR range 8000 0000h - 80FF FFFFh
    129: means DDR range 8100 0000h - 81FF FFFFh
    ...
    159: means DDR range 9F00 0000h - 9FFF FFFFh
    So, it in total 32*16MB each = 512 DDR range

    2. If you want to use .cfg
    Cache.setMarMeta(0x80000000, 0x20000000, Cache.PC | Cache.PCX | Cache.PFX | Cache.WTE);
    The first parameter is starting address, the second is length and the third is attribute,
    See: software-dl.ti.com/.../Cache.html

    3. This is to set L2 cache size to 256KB. L2 mode with 256 in .bld is the same, it is L2CFG register L2 mode field.

    4. This is to Writes back all modified cache lines in the processor’s internal cache to main memory and invalidates (flushes) the internal caches.

    5. L1D and L1P is setup as all cache by the SYSBIOS. You can check the value from L1PCFG and L1DCFG registers. Or you can use CSL function to get/set:

    CACHE_setL1DSize(), CACHE_getL1DSize(), CACHE_setL1PSize() and CACHE_getL1PSize().

    Regards, Eric
  • 0 in reply to lding
    Intellectual 475 points

    Hi,

    thanks for your reply.

    2. Ok, I deleted the source code lines, add this line to my cfg file and set the L2 cache size to 256K in my bld-file; but the L2 cache has not been set, yet (CACHE_getL2Size() returns 0 at runtime). Did I miss something?

    My .bld-file looks like:

    var Build = xdc.useModule('xdc.bld.BuildEnvironment');

Build.platformTable["ti.platforms.idkAM572X:dsp1"] = {
    externalMemoryMap: [
        [ "DSP1_PROG", {
            name: "DSP1_PROG", space: "code/data", access: "RWX",
            base: 0x86000000, len: 0x600000,
            comment: "DSP1 Program Memory (6 MB)"
        }],
    ],
    codeMemory:  "DSP1_PROG",
    dataMemory:  "DSP1_PROG",
    stackMemory: "DSP1_PROG",
    l1DMode: "32k",
    l1PMode: "32k",
    l2Mode: "256k"
};


/*
 *  ======== ti.targets.elf.C66 ========
 */
var C66 = xdc.useModule('ti.targets.elf.C66');
C66.ccOpts.suffix += " -mi10 -mo -pdr -pden -pds=238 -pds=880 -pds1110 ";
Build.targets.$add(C66);

    *EDIT*: I tried this in a minimal DSP project and it runs with L2 cache. My current project is more complex and uses libs. The problem may be in my project settings.

    3. I didn't understand the logic. I set the cache size to 256K, but allocate in DDR 512MB for cache. How are they related?

    5. In the Debug View of CCS for DSP, I cannot find any cache registers in the "Registers-View". Is this normal? A workaround is to look in memory browser: address 0184 0000h (L2CFG), 0184 0040h (L1DCFG) and 0184 0020h (L1PCFG), right?

    Best regards

    Thomas

    *EDIT*: I recognize, that my DSP memory (start: 0x8600_0000) and Cache memory in DDR (0x8000_0000 -  0x9FFF_FFFF) share the same region. Is this a problem?

  • 0 in reply to Thomas N.
    TI__Guru* 95265 points
    Hi,

    Sorry, I missed the thread.
    For 2) We have .bld example with l2mode setup under ti\drv\pm\example\core_loading\config\config_c66.bld, you can refer to.

    For 3) DDR3 is cached into L2. The DDR3 you made 512MB cache doesn't mean that the whole DDR3 is cached into L2 at one time. The code/data is cached per cache line size, it may cache multiple lines into the memory, but not the whole DDR.

    For 5) You can view them in CCS memory browser, not the CCS register view.

    Regards, Eric
  • 0 in reply to lding
    Intellectual 475 points
    Hi lding,

    no problem, thanks for your reply. Meanwhile, I'm familiar with the memory/cache configuration for TI boards with the help of CCS. Thank your very much for your help.

    Best regards
    Thomas