I've been starting to think about how we want to use caching for our new project using AM5728 and SysBios. Since we will have a very large project we will have to load the code in External RAM. My thought was to allocate all cache possible in L1 and L2. However, not all L2 is cacheable, so that will leave a small amount of L2 available for general use.
I updated my platform as shown below.
My linker.cmd file generated shows:
MEMORY
{
OCMC_RAM2 (RWX) : org = 0x40400000, len = 0x100000
OCMC_RAM1 (RWX) : org = 0x40300000, len = 0x80000
OCMC_RAM3 (RWX) : org = 0x40500000, len = 0x100000
L2SRAM (RWX) : org = 0x800000, len = 0x40000
EXT_RAM (RWX) : org = 0x80000000, len = 0x80000000
}
I guess I am surprised that the L2SRAM len is 256 KiB. On the AM5728 the L2 SRAM is 288-KiB. 256KiB can be cache leaving 32 KiB for SRAM. I guess I expected the L2 Cache setting of 256k to reduce the L2SAM available by 256k and in this case leave 0. So, I guess the L2SRAM under Custom Memory needs to be manually coordinated with the L2 Cache pulldown. True?
If that is the case, does the cache use the lower part or upper part of the memory?
In other words do I want
L2SRAM 0x00800000 0x00008000 <- 32KiB starting at 0x800000
or
L2SRAM 0x00840000 0x00008000 <- 32KiB starting at 256KiB above 0x800000