Part Number: PROCESSOR-SDK-DRA8X-TDA4X
We are trying to implement ECC for LPDDR4 RAM and need support to configure inline ECC of DDRSS module.
Details are:
Hardware Setup:
- CCS
- Spectrum Degital XDS560V2 STM USB Emulator
- EVM J721E_DRA829_TDA4VM
- PDK having GEL file to flash
We understood that, we have to enable inline ECC module of MSMC2DDR bridge in DDRSS module which will give us ECC capability in LPDDR4.
Is our understanding correct?
While referring TI TDA4x TRM document we have found steps which are below,
- Enable ECC in GEL file
- SET DDRSS_ECC_CTRL_REG bit[0] and bit[1]. which should be before loading data into LPDDR4
- Specify start and end address range in DDRSS_ECC_R0_STR_ADDR_REG and DDRSS_ECC_R0_END_ADDR_REG. In those register only bit{18:0] are usable and [31:19] are reserved. Now LPDDR4 start address is 0x80000000. How to write this start address in the [18:0] bits? Same question for end address.
- How to set interrupt for SEC and DEC and how to route it into MCU domain?
- Do i need to configure anything else?
- Initialize LPDDR4 (already there in GEL file)
- Load firmware
- Enable ECC check in boot process DDRSS_ECC_CTRL_REG bit[2]
Any help appreciated
