Compiler/TDA4VM: Are there write protection restrictions on the operation of the CTRLMMR_PCIE_REFCLK1_CLKSEL register?

Hi，

By modifying the LOCK register, I can modify the CTRLMMR_PCIE_REFCLK1_CLKSEL register. The question now is, I modified the register, but the PCIe clock is not output? What should I do next?

Best Regards

Kepei

Hi Kepei,

Where did you probe for the clocks in the EVM? As for the configurations, there are only CTRLMMR_PCIE_REFCLK1_CLKSEL and CTRLMMR_ACSPCIE1_CTRL to be configured.

Thanks

Kishon

Hi Kishon，

Thanks for your reply！

What does "Where did you probe for the clocks in the EVM?" mean?

I configured the register CTRLMMR_PCIE_REFCLK1_CLKSEL  to 0x101 and CTRLMMR_ACSPCIE1_CTRL  to 0x01000000 through the k3config write command after linux started, but there is no clock output.

Thanks！

Kepei

Hi Kepei,

I'm trying to understand how you are saying there is no clock output? Where did you probe the clock signals?

Thanks

Kishon

Hi Kishon,

I used an oscilloscope to measure the output signal of the oscilloscope, and the ground and probe of the oscilloscope respectively measured the 2 pins of the differential signal PCIE_REFCLK1P and PCIE_REFCLK1N.

Thanks

Kepei

I also tried connecting the ground of the oscilloscope to GND, and the probes were connected to PCIE_REFCLK1N and PCIE_REFCLK1P, there was no signal too.

Hi Kepei,

Did you also made the necessary board modifications to route to the connector? Since you have mentioned TDA4VM in the subject, I think it's the same EVM provided by TI?

Thanks

Kishon

Hi Kishon，

The following is the schematic diagram. TDA4VM_A provides the clock to TDA4VM_B, the clock signal I tested on the pull-down resistor of the clock pin.

The circuit principle is the same as EVM, except that EVM is a PCI clock provided by an external clock, so there is no solder pull-down resistor.

Thanks

Kepei

Kepei,

Thanks! I'll have to check this internally.

Regards

Kishon

Hi Kishon，

Okay, thank you very much and look forward to your answer.

Regards

Kepei

Hi Kishon，

Have you completed the test on the EVM board?

Regards

Kepei

Hi Kepei,

We haven't yet been able to do the board modification. Meanwhile after reviewing, I have the following patch. Please use the attached patch (in addition to control module register modification) and check if you see any clocks?

Thanks

Kishon

From d83bdd855d02d34ec8e5dc5258e250c9be355004 Mon Sep 17 00:00:00 2001
From: Kishon Vijay Abraham I <kishon@ti.com>
Date: Wed, 6 Jan 2021 14:11:47 +0530
Subject: [PATCH] route_external_fix

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 drivers/phy/cadence/phy-cadence-sierra.c | 58 ++++++++++++++++++++++++
 1 file changed, 58 insertions(+)

diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index 309aa30f1c03..96452e5ee8bc 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -28,6 +28,7 @@
 #define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG		0x49
 #define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG		0x4A
 #define SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG		0x4B
+#define SIERRA_CMN_PLLLC_CLK1_PREG			0x4D
 #define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG		0x4F
 #define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG		0x50
 #define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG	0x62
@@ -144,12 +145,22 @@
 #define SIERRA_MAX_LANES				16
 #define PLL_LOCK_TIME					100000
 
+#define SIERRA_PHY_PMA_COMMON_OFFSET(block_offset)	\
+				     (0xE000 << (block_offset))
+#define PHY_PMA_CMN_CTRL1				0x0000U
+
 static const struct reg_field macro_id_type =
 				REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15);
 static const struct reg_field phy_pll_cfg_1 =
 				REG_FIELD(SIERRA_PHY_PLL_CFG, 1, 1);
 static const struct reg_field pllctrl_lock =
 				REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0);
+static const struct reg_field phy_pma_cmn_ctrl_rcv_out_en =
+				REG_FIELD(PHY_PMA_CMN_CTRL1, 6, 7);
+static const struct reg_field cmn_plllc_clk1outdiv =
+				REG_FIELD(SIERRA_CMN_PLLLC_CLK1_PREG, 0, 6);
+static const struct reg_field cmn_plllc_clk1_en =
+				REG_FIELD(SIERRA_CMN_PLLLC_CLK1_PREG, 12, 12);
 
 struct cdns_sierra_inst {
 	struct phy *phy;
@@ -193,10 +204,14 @@ struct cdns_sierra_phy {
 	struct reset_control *apb_rst;
 	struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES];
 	struct regmap *regmap_phy_config_ctrl;
+	struct regmap *regmap_phy_pma_common_cdb;
 	struct regmap *regmap_common_cdb;
 	struct regmap_field *macro_id_type;
 	struct regmap_field *phy_pll_cfg_1;
+	struct regmap_field *phy_pma_cmn_ctrl_rcv_out_en;
 	struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES];
+	struct regmap_field *cmn_plllc_clk1outdiv;
+	struct regmap_field *cmn_plllc_clk1_en;
 	struct clk *clk;
 	struct clk *cmn_refclk_dig_div;
 	struct clk *cmn_refclk1_dig_div;
@@ -268,6 +283,14 @@ static struct regmap_config cdns_sierra_phy_config_ctrl_config = {
 	.reg_read = cdns_regmap_read,
 };
 
+static struct regmap_config cdns_sierra_phy_pma_cmn_config = {
+	.name = "sierra_phy_pma_cmn",
+	.reg_stride = 1,
+	.fast_io = true,
+	.reg_write = cdns_regmap_write,
+	.reg_read = cdns_regmap_read,
+};
+
 static int cdns_sierra_phy_init(struct phy *gphy)
 {
 	struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
@@ -417,6 +440,20 @@ static int cdns_regfield_init(struct cdns_sierra_phy *sp)
 	}
 	sp->macro_id_type = field;
 
+	field = devm_regmap_field_alloc(dev, regmap, cmn_plllc_clk1outdiv);
+	if (IS_ERR(field)) {
+		dev_err(dev, "cmn_plllc_clk1outdiv reg field init failed\n");
+		return PTR_ERR(field);
+	}
+	sp->cmn_plllc_clk1outdiv = field;
+
+	field = devm_regmap_field_alloc(dev, regmap, cmn_plllc_clk1_en);
+	if (IS_ERR(field)) {
+		dev_err(dev, "cmn_plllc_clk1_en field init failed\n");
+		return PTR_ERR(field);
+	}
+	sp->cmn_plllc_clk1_en = field;
+
 	regmap = sp->regmap_phy_config_ctrl;
 	field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1);
 	if (IS_ERR(field)) {
@@ -425,6 +462,14 @@ static int cdns_regfield_init(struct cdns_sierra_phy *sp)
 	}
 	sp->phy_pll_cfg_1 = field;
 
+	regmap = sp->regmap_phy_pma_common_cdb;
+	field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_rcv_out_en);
+	if (IS_ERR(field)) {
+		dev_err(dev, "phy_pma_cmn_ctrl_rcv_out_en field init failed\n");
+		return PTR_ERR(field);
+	}
+	sp->phy_pma_cmn_ctrl_rcv_out_en = field;
+
 	for (i = 0; i < SIERRA_MAX_LANES; i++) {
 		regmap = sp->regmap_lane_cdb[i];
 		field = devm_regmap_field_alloc(dev, regmap, pllctrl_lock);
@@ -478,6 +523,15 @@ static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp,
 	}
 	sp->regmap_phy_config_ctrl = regmap;
 
+	block_offset = SIERRA_PHY_PMA_COMMON_OFFSET(block_offset_shift);
+	regmap = cdns_regmap_init(dev, base, block_offset, reg_offset_shift,
+				  &cdns_sierra_phy_pma_cmn_config);
+	if (IS_ERR(regmap)) {
+		dev_err(dev, "Failed to init PHY PMA common CDB regmap\n");
+		return PTR_ERR(regmap);
+	}
+	sp->regmap_phy_pma_common_cdb = regmap;
+
 	return 0;
 }
 
@@ -651,6 +705,10 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev)
 	if (!sp->autoconf && sp->nsubnodes > 1 && !already_configured)
 		regmap_field_write(sp->phy_pll_cfg_1, 0x1);
 
+	regmap_field_write(sp->phy_pma_cmn_ctrl_rcv_out_en, 0x3);
+	regmap_field_write(sp->cmn_plllc_clk1_en, 0x1);
+	regmap_field_write(sp->cmn_plllc_clk1outdiv, 0x2e);
+
 	pm_runtime_enable(dev);
 	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
 	return PTR_ERR_OR_ZERO(phy_provider);
-- 
2.17.1

Hi Kishon

Thank you so much for your prompt reply!

Is this patch file based on psdk-7.1?

Thanks

Kepei

Hi Kepei,

yes.. it's based on 5.4 kernel.

Thanks

Kishon

Hi Kishon，

I tested it according to your suggestion;

1. Added the patch you provided;

2. Recompile the kernel;

3. Replace the Image file;

4. Start linux;

5. The k3conf write command unlocks the register;

6.k3conf write 0x00108074 0x101 command to modify the CTRLMMR_PCIE_REFCLK1_CLKSEL register

7.k3conf write 0x00118094 0x01000000 modify the CTRLMMR_ACSPCIE1_CTRL register

But unfortunately, there is still no clock output on the pin.

If possible, can you test it on the EVM board?

Thanks

Kepei

Hi Kishon，

Do you have the results of the test on EVM? Or any suggestions?

Regards

Kepei

Hi，Kishon，

Are there any updates on your solution to this problem?

Thanks

Kepei

Kepei,

We are working on this and we should have an update in the next few days.

Regards

Karthik

Hi Karthik，

Alright, thank you very much!

Looking forward to your results.

Thanks

Kepei

Kepei,

Can you confirm if you rescaned the PCIe bus after enabling clock?

I received my modified EVM and did a quick try with the patch, I was not able detect the SSD on the M2 slot. But one suspect is that the RC PLL shall be locked before he can gave out clock. could you try the same sequence on your side:

M.2 slot ====================================

//enable PADs of ACSPCIe

devmem2 0x00118094 w 0x01000000

//unlock CTRLMMR_LOCK2 for 8000h to 9FFFh

devmem2 0x00109008 w 0x68EF3490

devmem2 0x0010900C w 0xD172BC5A

//refclk select for ACSPCIe

devmem2 0x00108078 w 0x00000100

echo 1 > /sys/bus/pci/devices/0002:00:00.0/remove

echo 1 > /sys/bus/pci/rescan

I will sync up with Kishon and we may need to add these two registers in the patch to get the correct sequence. 

regards

Jian

Hi Jian，

I'm very sorry, because some other work caused the delay. I just tested your suggestion, but there is still no clock output.

j7-evm login: root
Last login: Thu Nov 19 18:09:28 UTC 2020
root@j7-evm:~# devmem2 0x00118094 w 0x01000000
/dev/mem opened.
Memory mapped at address 0xffff95cd0000.
Read at address  0x00118094 (0xffff95cd8094): 0x01000003
Write at address 0x00118094 (0xffff95cd8094): 0x01000000, readback 0x01000000
root@j7-evm:~# devmem2 0x00109008 w 0x68EF3490
/dev/mem opened.
Memory mapped at address 0xffff95fb0000.
Read at address  0x00109008 (0xffff95fb9008): 0x00000000
Write at address 0x00109008 (0xffff95fb9008): 0x68EF3490, readback 0x68EF3490
root@j7-evm:~# devmem2 0x0010900C w 0xD172BC5A
/dev/mem opened.
Memory mapped at address 0xffffb90a0000.
Read at address  0x0010900C (0xffffb90a900c): 0x00000000
Write at address 0x0010900C (0xffffb90a900c): 0xD172BC5A, readback 0xD172BC5A
root@j7-evm:~# devmem2 0x00108078 w 0x00000100
/dev/mem opened.
Memory mapped at address 0xffffb6670000.
Read at address  0x00108078 (0xffffb6678078): 0x00000000
Write at address 0x00108078 (0xffffb6678078): 0x00000100, readback 0x00000100
root@j7-evm:~# echo 1 > /sys/bus/pci/devices/0000\:00\:00.0/remove 
[  639.633076] pci_generic_config_write32: 20 callbacks suppressed
[  639.633084] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0x84 may corrupt adjacent RW1C bits
[  639.648797] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0xdc may corrupt adjacent RW1C bits
[  639.658617] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0xc8 may corrupt adjacent RW1C bits
[  639.668432] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0x92 may corrupt adjacent RW1C bits
[  639.678155] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0x9c may corrupt adjacent RW1C bits
[  639.687972] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0x92 may corrupt adjacent RW1C bits
[  639.697723] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0x4 may corrupt adjacent RW1C bits
[  639.707427] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0x4 may corrupt adjacent RW1C bits
[  639.717112] pci_bus 0000:01: busn_res: [bus 01] is released
root@j7-evm:~# echo 1 > /sys/bus/pci/rescan 
[  654.149076] pci 0000:00:00.0: [104c:b00d] type 01 class 0x060400
[  654.155149] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0x4 may corrupt adjacent RW1C bits
[  654.164813] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0x4 may corrupt adjacent RW1C bits
[  654.174486] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0x92 may corrupt adjacent RW1C bits
[  654.184216] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0xb2 may corrupt adjacent RW1C bits
[  654.193969] pci 0000:00:00.0: supports D1
[  654.197968] pci 0000:00:00.0: PME# supported from D0 D1 D3hot
[  654.203707] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0x84 may corrupt adjacent RW1C bits
[  654.215396] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0x3e may corrupt adjacent RW1C bits
[  654.227230] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0x3e may corrupt adjacent RW1C bits
[  654.236995] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0x3e may corrupt adjacent RW1C bits
[  654.246730] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0x3e may corrupt adjacent RW1C bits
[  654.256470] pci 0000:00:00.0: PCI bridge to [bus 01]
[  654.261430] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0x1c may corrupt adjacent RW1C bits
[  654.271449] pcieport 0000:00:00.0: PME: Signaling with IRQ 36
[  654.277723] pcieport 0000:00:00.0: AER: enabled with IRQ 36

Thank you very much for your help!

Kepei

Hi

Update my test status again.

The previous kernel dump status may be caused by overheating of the chip.

After cooling the chip again, I started TDA4_A as the RC side, and executed the operation provided by Jian.

At present, I can read and write the ep device on the TDA4_B side normally. Thank you very much for your help.

My next question is, can I implement these manual operations in the Linux driver or device tree?

Regards

Kepei