• State Resolved
  • Locked Locked
  • Replies 9 replies
  • Subscribers 99 subscribers
  • Views 475 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

AM5716: DDR Interface Debug

AM5716: DDR Interface Debug - Proper board routing edition!

Jason Bender1
Prodigy 210 points

Part Number: AM5716

Hi,

I would like to continue a discussion that is now locked.  I got a lot of excellent feedback and very much appreciate everything Kevin S was able to offer!
e2e.ti.com/.../am5716-ddr-interface-debug

I am currently re-designing the board and appreciate feedback from anyone willing to offer it.  I've attached a spreadsheet showing all the trace lengths, skew, and stub lengths.
I will certainly match all the pair lengths (as I should have done to begin with), as that is pretty easy.  I'll address skew in the signal groups as best I can..  In particular the stub lengths seem like they will be difficult to get down to the very small lengths specified.

I'm looking for any direction from those in the field might, whether part of TI or not.  I could really use some help here to understand what rules I can bend a bit and what are critical.  Perhaps others are layout wizards, but I'm finding it difficult to match ALL the specs.  I am certainly not looking for anyone to design this for me, just basic direction.  Thank-you!

-Jason Bender

3441.DDR Trace Lengths.xlsx

  • 0
    TI__Guru 54705 points

    Can you be more specific regarding which requirements you are unable to meet?

  • 0 in reply to Robert Eschler
    Prodigy 210 points

    Hi Robert,

    Sure.  I am referencing SPRS957G, Table 8-13 and and 8-14.  In particular the AS length (CARS38) and the AT length (CARS312).  These are specified in picoseconds, which I convert to distance using 1pS = 5 mils (hopefully that is correct?)

    STUB LENGTH - Using that conversion, the stub lengths should be between 5-17 pS --> 25-85 mils.  Mine are as much as 6mm (or 236 mils).  This is the one that is going to be the toughest, I think, given that I am using the top and bottom layers only, using 4mil trace / 8mil spacing.

    TERMINATION LENGTH - The termination length should be (typ) 75 pS --> 375 mils.  Mine are as much as 25mm (or 1000mils).  It seems I've done something wrong / non-standard here, but I'm not sure what.  I used a resistor array and needed the space to fan out to those.  I'm entirely open to finding that I'm on the wrong track here...  Note, I was trying to avoid very small 0201 devices, but maybe that is what needs to be done.

    Otherwise, I will length match all the differential signals, and improve on matching DQS signals to the byte lanes and DB's within a byte.  All in all, it would be nice if someone could point out something I did that is a clear "no-go" to give me some confidence that I can make this work the next time around.

    As if it wasn't obvious I don't have a resource available to me to review my design, so your help (and patience) is always appreciated!

    -Jason

  • 0 in reply to Jason Bender1
    TI__Guru 54705 points

    The stub length can be increased, but as recommended in the DM, if this is done - it is strongly recommended to perform signal integrity analysis. (IBIS models for IO should be available on TI.com).  You are increasing significantly above recommendation (3x) so strongly suggest simulations.  Similar feedback regarding the increase of the termination length.  While it might not be as critical when increasing termination length - again you are increasing significantly (3x).  Yes using R-packs versus individual resistors probably causes some increase.  Make sure to optimize R-pack assignments.  Have you reviewed the EVMs routings?  I understand your limitations (top/bottom routing only)...that certainly not case with EVM.

  • 0 in reply to Robert Eschler
    Prodigy 210 points

    Hi Robert,

    Thank-you.  Are the IBIS models used with pspice, or would this typically be done using some other simulation software?  If there is not a high cost barrier to doing the simulation, I certainly will.  Ideally, I would like to follow the guidelines and not be on the margins with my design to begin with - so the 'rules of thumb' you're offering are very useful.

    I had mistakenly thought that stripline routing was not recommended by TI, and avoided putting any signals on the inner layers (I read this in  SPRAAR7H and conflated this to mean all DDR signals.)  Since I thought all routing had to be Top/Bottom only, I certainly found it difficult!  As I've found in engineering, many times the key to a good design is to figure out which requirement needs to be relaxed, as is certainly the case here.  Thank-you for telling me this.  I'll look at the EVM routing to see what was done there, as I should have done earlier (I use Kicad and the .brd file does not import, but I'll figure out how to get that opened).

    As I go from one layer to another, should I be placing a via very close by?  I think this might have been a detail I did not fully appreciate - basically the return path length is just as important for the high speed signal timing?  Should I keep the differential signals (DQS's and CLK) as microstrip routing?  Looks like timing is slowed by ~10% for stripline?

    As a general rule, is it highly recommended to have the boards built with a controlled impedance?  Perhaps this has changed over time as manufacturing process have improved.  Knowing where the industry is along the spectrum of "of-course, it won't work without it" and "to really do it right, yes, but probably not necessary as long as your fab house is up-to-date" would be helpful.

    Finally, could you clarify what you mean by "optimize R-pack assignments"?  I'm afraid I don't understand.

    Thank-you, again!
    -Jason

  • 0 in reply to Robert Eschler
    Prodigy 210 points

    Hi Robert,

    If you have a chance, any feedback on the above questions is appreciated.  Thank-you!

    -Jason

  • +1 in reply to Jason Bender1
    TI__Guru 54705 points

    The IBIS models are not a spice model, but a model of the IO behavior.  It can be used with variety of PCB simulation packages.  Yes, 'rule-of-thumb' is how the Jacinto6 DDR interfaces where supported.  We tried to simplify the DDR PCB design with the rules, which keeps the customer from having to deal with more complicated PCB design analysis (less simulation, timing, etc).

    I think SPRAAR7H is targeted more for high speed differential interfaces.  While the same concepts to apply to DDR interface, I would recommended following the guidance in the AM57x data manual.  GND vias are likely not necessary near each via transition.  Most transitions should be near either the AM57 or Memory device - and the GND pins should have via.  If you have a layer transition away from the packages, you can put GND via...it certainly won't hurt.  But likely not a show-stopper.

    The DQS signals are part of a BYTE group (see Data manual) and should be routed on same layer as other signals in that group.  There are 4 separate byte groups, each including DQSp, DQSn, DQM, and 8bit of D.  Similarly, the CLK signals are part of the Address/Control group, and should be routed on same layer as other signals in that group.  This all detailed in the DM.

    Yes - control impedance is required.  The suggested impedance ranges in documented in DM.

  • 0 in reply to Robert Eschler
    Prodigy 210 points

    Thank-you for the feedback.  It is much appreciated.

  • 0 in reply to Jason Bender1
    TI__Guru 54705 points

    If this answers your question, can we close this ticket?

  • 0 in reply to Robert Eschler
    Prodigy 210 points

    Hi Robert,

    Yes, you can close the ticket.  Thank-you for your help!