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Hello, I am following your design ZCU102_AFE79xx_64b66b_12Gbps, and I have a question. In your project you define a vector with only 64 samples, but is it possible to have a vector to trasmit with more than 64 samples? If it is, do I have to make a lot of changes in the FPGA code?
I am new on JESD204 interface so I am not sure if this is a limitation from the interface or from the code that you provide.
Thank you!
