Other Parts Discussed in Thread: AFE7900, LMK04828
Tool/software:
Dear Team,
We are using AFE7906 in our design as per latte we have generated the .c file ( .py file tested the configuration with EVM) and loading the file to AFE device as per bring up flow chart, We observed that 171 register expected value not received so poll bit starts loop for 10000 times and then device configuration register not written. We successfully checked device id and version etc..
In register map 171h mentioned as DBG_ASYNC_FIFO_SYSREF_SPACING
What is the purpose of this register?
Whatever AFE7900 EVM design we followed same terminations for clock and SYSREF also same PLL device LMK04828 we used.
Kindly do the needful.
