Other Parts Discussed in Thread: LMK04828, AFE7950
Tool/software:
Our setup:
- AMD ZCU102
- two TI AFE7950EVM
- external clock
Both LMK04828 are fed from the same clock and get synchronised. This results in a synchronized REFCLK and SYSREF between both AFE7950EVM. SYSREF is on permanently.
We use the options
-
useSpiSysref = False
-
continuousSysref = True
According to the manual, this should ensure deterministic latency, but we observe changing phase relationships between the carrier frequencies (currently 2.2 GHz), if one AFE7950 is reconfigured. We expected all PLL dividers to be reset due to the synchronized SYSREF.
Is it possible to get deterministic phase relationship between the carriers with this setup? What's the problem here?