Hi dear supporting team,
My customer uses TRF3722 in their product and they found several devices PLL might go unlock under cold temperature. After doing several tests, they found the unlock devices is related to 1911 batch.
We have done below tests:
1. For devices that are not 1911 batch. Configure TRF3722 under room temp several times, i.e. calibrate VCO several times under room temp. The vtune voltage will vary within very small range:
Freq=1554MHz. Other batch device: Vtune voltage is from 1.1~1.2V
|
Test times |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
|
VTune/V |
1.235 |
1.212 |
1.201 |
1.195 |
1.188 |
1.182 |
1.177 |
1.18 |
1.172 |
1.168 |
2. For device that is 1911 batch.
Freq=1554MHz, Configure TRF3722 under room temp several times, i.e. calibrate VCO several times under room temp. The vtune voltage will vary within large range.
Vtune voltage is around 0.8~1.3V
|
test times |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
17 |
18 |
|
VTune/V |
0.82 |
1.35 |
0.78 |
1.338 |
1.333 |
0.76 |
1.317 |
0.781 |
1.326 |
1.316 |
1.314 |
1.308 |
1.304 |
1.302 |
1.3 |
0.741 |
1.295 |
0.755 |
3. For 1911 batch device, run temperature test. calibrate VCO under room temp, and sweep temp. When temperature reaches to cold temp, we found LD pin will go unlock and go lock, back an forth. We also monitor the Vtune voltage, it shows Vtune goes to 3.2V. Below is Vtune voltage under different temp:
|
Temp/℃ |
Vtune/V |
|
|
55 |
1.051 |
|
|
-40 |
3.214 |
|
|
25 |
1.442 |
If we increase the temperature to higher, PLL will go locked again.
4. For 1911 device, when PLL goes unlock under cold temp, set Reg2 bit31 EN_CAL to 1, PLL will become locked.
5. We have soldered the device to TI TRF3722EVM, we will see similar unlock issue under cold temp.
There are several questions needs to be checked:
1. What is the proper Vtune voltage range under room temp if calibrate VCO?
2. What is the Vtune voltage range across whole temp, from -40C to 85C to maintain PLL locked?
3. During VCO calibration, how VCO chooses cap? How to make sure PLL chooses right cap code to make sure PLL can maintain locked across temperautre?
4. Shall we send back this device for further analysis?
Thanks a lot for your support!
Best regards,
Joyce Li
