HI all，
I have come across a weird problem on my board,JTX is ADC,JRX is FPGA,and the jesd204c link between them is established OK, then i sampled the NSD in each channel with no signal added to the ADC input, I find that some channels have received large signals. I sampled down the data and draw a picture ,i find that it is a signal that raises the whole bottom noise.I have checked the PRBS,there is no error.And the FPGA loopback is also ok. What may be the problem?
The picture is attached.
Thanks.
