• State TI Thinks Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 2 answers
  • Subscribers 10 subscribers
  • Views 481 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DAC38RF80: details about error status

bala tokala
Prodigy 90 points
Part Number: DAC38RF80
Other Parts Discussed in Thread: , LMK04832

I am using dac38rf80 and I am getting JESD alarms on registers 0x64 to 0x6b as 0x2000.

1. In which scenario link configuration error will be set by dac and how to resolve this alarms.

2 . Not able to establish JESD link with DAC is it the reason?

we are using our custom board.

dac configuration :-

input_clk :- 300 MHZ
using on chip pll
dac clock frequency :- 9000MHZ
DUAL DAC
2 IQ pairs per dac
4 serdes lanes per dac
interpolation x24
serdes rate 7.5gbps
sysref frequency 6.25MHZ
k = 30

  • 0
    TI__Genius 13740 points

    Hi Bala,

    I tested this configuration on a DAC38RF80EVM and did not see the same errors. Could you share the exact register settings you are using? This would help me test the same configuration that you are using.

    Are you using the same source for your clock and sysref? Sysref should be synchronous with the DACCLK.

    Regards,

    David

  • 0 in reply to David Chaparro
    Prodigy 90 points

    Hi David ,

       Thanks for fast response.

     1.yes, we are using same source for clocks as LMK04832 . but I have not synchronised the rising edge of both . will this cause any problem ? 

     2. still I want to know in which scenario DAC can raise that alarm. there is nothing much about that in data sheet.

    I am attaching the register configurations . please review them once .

    dac_38rf80_cofig_9000msps.txt 
      0x0  0xD803
  0x0  0x5803
  0x01 0x1880
    x09	x0000
    x01	x1880
    x00	x5803
    x00	x5803
    x09	x0004
    x31	x0008
    x32	x0e08
    x33	xc418
    x31	x0008
    x31	x0408
    x0b	x0002
    x3b	x8002
    x3b	xa802
    x33	xc418
    x3c	x8229
    x3c	x8229
    x3c	x8229
    x3c	x8229
    x3c	x8229
    x3c	x8229
    x31	x0408
    x3b	xa802
    x32	x0e08
    x0c	xa002
    x09	x0001
    x25	x3a00
    x25	x6a00
    x09	x0002
    x25	x6300
    x25	x6a00
    x09	x0004
    x0b	x0002
    x0c	xa002
    x0c	xa002
    x24	x1000
    x33	xc418
    x09	x0001
    x4a	x0103
    x5f	x0123
    x4a	x0303
    x5f	x3223
    x4a	x0703
    x5f	x3213
    x4a	x0f03
    x5f	x3210
    x4a	x0f03
    x60	x5567
    x4a	x0f03
    x60	x5767
    x4a	x0f03
    x60	x5767
    x4a	x0f03
    x60	x5764
    x09	x0004
    x3e	x0909
    x09	x0002
    x4a	x0003
    x5f	x5123
    x4a	x0003
    x5f	x5723
    x4a	x0003
    x5f	x5763
    x4a	x0003
    x5f	x5764
    x4a	x1003
    x60	x4567
    x4a	x3003
    x60	x3267
    x4a	x7003
    x60	x3217
    x4a	xf003
    x60	x3210
    x09	x0001
    x4e	x0f0f
    x4d	x0100
    x4e	x0f0f
    x4d	x0300
    x4c	x1d03
    x4c	x1d03
    x4b	x1301
    x4a	x0f03
    x09	x0002
    x4e	x0f0f
    x4d	x0100
    x4e	x0f0f
    x4d	x0300
    x4c	x1d03
    x4c	x1d03
    x4b	x1301
    x4a	xf003
    x09	x0001
    x0a	x0cb0
    x0a	x8cb0
    x09	x0002
    x0a	x82b0
    x0a	x8cb0
# disable the sysref configuration in clk path
    0x09 0x3 
    0x24 0x0 
# disable the sysref configuration for jesd synchronization
     0x5c 0x0 
# use sysref to sync the clock divider
     0x09 0x4 
     0x0a 0xf003 
after 1000ms 
     0x0a 0x7003 
# put jesd to initialization state 
      0x00 0x5803
 # Skip one SYSREF pulse then use only the next one
      0x09 0x3 
      0x24 0x20 
      0x5c 0x03 
# release jesd for link up using single link only for 2 dac's 
      0x00 0x5800

  • 0 in reply to bala tokala
    TI__Genius 13740 points

    Hi Bala,

    1. It can cause problems if you need deterministic latency.

    2. Mismatches in any of the JESD configuration parameters will cause a link configuration error.

    Regards,

    David

  • 0 in reply to David Chaparro
    Prodigy 90 points

    Hi David,

       Any comments on configuration registers and sequence.

  • 0 in reply to bala tokala
    TI__Genius 13740 points

    Hi Bala,

    In regards to my last reply, the link configuration error can be caused when the JESD configuration parameters do not match between the FPGA and the DAC.

    One note I have on your configuration registers is that it would be better to only write to a register once. Also, when I configure my DAC I set register 0x0A to 0x8C10.

    Regards,

    David