DAC38RF83: several questions about dac38rf83

Xiao,

The easiest way to see if the DAC PLL is working is to check the loop filter voltage value, which is page 0, address 0x6, bits 7:5. If the PLL is working properly, these three bits should report a decimal value between 3 and 5. If the PLL is not locked, this value will be either 0 or 7 decimal.

Another check is to place the part in NCO only mode. If the NCO output is at the proper frequency, the DAC PLL is operating properly.

If you have access to the CLKTX output, this also will tell you if the PLL is operating properly or not.

Make sure miscellaneous register 0x3B (page 4) has bit 15 set to "1". This bit determines if the DAC is to use the PLL or an external clock.

Regards,

Jim   

Hi, Jim:

   The miscellaneous register 0x3B (page 4) has bit 15  indeed  is set to "1".

   The miscellaneous register 0x31 (page 4) has bit 10  indeed  is set to "1".

   The miscellaneous register 0x0C (page 4) has bit 0   indeed  is set to "0" (There are no reference about it ,I don't know exact meaning aobut it).

   Also there is a file attached in the post, can you check it and give extra help ?

   Thanks

Xiao,

I will look at your file. What is the status of register 0x6 page 0? Also if the PLL is unlocked, register 0x0B in page 4 will report a "1" in bit 0. What is the status of this register?

Regards,

Jim  

register 0x06   page 0  = 0x3D02

register 0x0B  page 4   = 0x0002

Are you tuning the VCO? This must be done to get the PLL to lock. The GUI does this function when you click on PLL Auto Tune.

I made a mistake. I need you to read back register 0x05. From what I am seeing from register 0x06, the VCO is not locked. 

Hi,Jim:

register 0x05   page 0  = 0x0139 (before I read register 0x5@page 0, I clear all fields of register 0x5 to make sure that it is not a sticked value)

Yes , I tried to tune the VCO. But I will double check the tuning sequences right now.

Best Regards

Xiao,

Your assumption regarding the temp sense read back is correct. 29d = 29 C.

Your PLL is not locked since bit 0 of add 0x5 = 1. Are you providing a 512MHz reference clock to the DAC? Is this single-ended or differential? What is the amplitude? Make sure the values in page 4 of address 0x31 are set properly. 

Regards,

Jim 

I provide reference clock to the DAC .It is a differential LVPECL clock from LMK05318. The differential  amplitude is above 800mV. Register 0x31 @ page 4 is set 0x0400.

In your word document you sent, it shows a N divider value of 2. If this is true, register 0x31 should be set to 0x0408, not 0x0400 that you reported. 

512M_ref_pll_821.cfgXiao,

I have my PLL locked on my EVM using your settings with an external 512MHz diff clock. The config file is attached. Give this a try.

Regards,

Jim