Hello,
I am working with the AFE7769EVM and the TSW14J57 following the User Guide given sbau333b_AFE77xx_UserGuide. When I get to step 4.5 Program AFE77xx-EVM to program the first Default parameters Config1, I have an error on the JESD link. Below is the error log frome the Latte software: I have highlighted the part from which the errors begin.
What seems to be the problem? The check status interface of Latte gives me green lights on the JESD Rx status.
Thank you for your help,
Regards,
Theophile Delaroche
#====== #Executing .. AFE77xx/bringup/setup.py #Start Time 2020-10-19 18:21:44.749000 AFE77xxLibraryPG1P1 spi - USB Instrument created. resetDevice Purge MPSSE mode set Kintex RegProgrammer - USB Instrument created. Kintex RegProgrammer - USB Instrument created. #Done executing .. AFE77xx/bringup/setup.py #End Time 2020-10-19 18:21:48.947000 #Execution Time = 4.19799995422 s #================ ERRORS:0, WARNINGS:0 ================# #====== #Executing .. AFE77xx/bringup/devInit.py #Start Time 2020-10-19 18:21:53.063000 Successfully Loaded the Libraries. 8114 #Done executing .. AFE77xx/bringup/devInit.py #End Time 2020-10-19 18:22:22.293000 #Execution Time = 29.2300000191 s #================ ERRORS:0, WARNINGS:0 ================# #====== #Executing .. AFE77xx/bringup/basicBringup_Case-1.py #Start Time 2020-10-19 18:22:45.229000 DONOT_OPEN_Afe77xxPG1p1_FULL - Device registers reset. chipType: 0xa chipId: 0x77 chipVersion: 0x11 2T2R1F Number: 0 Valid Configuration: True laneRateRx: 9830.4 laneRateFb: 9830.4 laneRateTx: 9830.4 2T2R1F Number: 1 Valid Configuration: True laneRateRx: 9830.4 laneRateFb: 9830.4 laneRateTx: 9830.4 LMK Clock Divider - Device registers reset. lmk.writeReg(000,0x00000080) lmk.writeReg(000,0x00000000) LMK Clock Divider - Device registers reset. lmk.writeReg(000,0x00000080) lmk.writeReg(000,0x00000000) lmk.writeReg(000,0x00000080) lmk.writeReg(000,0x00000000) lmk.writeReg(330,0x00000033) lmk.writeReg(000,0x00000000) lmk.writeReg(002,0x00000000) lmk.writeReg(256,0x00000008) lmk.writeReg(257,0x00000055) lmk.writeReg(259,0x00000001) lmk.writeReg(260,0x00000020) lmk.writeReg(261,0x00000000) lmk.writeReg(262,0x000000F0) lmk.writeReg(263,0x00000044) lmk.writeReg(264,0x00000066) lmk.writeReg(265,0x00000055) lmk.writeReg(267,0x00000001) lmk.writeReg(268,0x00000020) lmk.writeReg(269,0x00000000) lmk.writeReg(270,0x000000F0) lmk.writeReg(271,0x00000044) lmk.writeReg(272,0x00000008) lmk.writeReg(273,0x00000055) lmk.writeReg(275,0x00000000) lmk.writeReg(276,0x00000000) lmk.writeReg(277,0x00000000) lmk.writeReg(278,0x000000F9) lmk.writeReg(279,0x00000000) lmk.writeReg(280,0x00000018) lmk.writeReg(281,0x00000055) lmk.writeReg(283,0x00000000) lmk.writeReg(284,0x00000020) lmk.writeReg(285,0x00000000) lmk.writeReg(286,0x000000F9) lmk.writeReg(287,0x00000000) lmk.writeReg(288,0x00000010) lmk.writeReg(289,0x00000055) lmk.writeReg(291,0x00000000) lmk.writeReg(292,0x00000000) lmk.writeReg(293,0x00000000) lmk.writeReg(294,0x000000F9) lmk.writeReg(295,0x00000011) lmk.writeReg(296,0x00000008) lmk.writeReg(297,0x00000055) lmk.writeReg(299,0x00000000) lmk.writeReg(300,0x00000000) lmk.writeReg(301,0x00000000) lmk.writeReg(302,0x000000F9) lmk.writeReg(303,0x00000000) lmk.writeReg(302,0x00000011) lmk.writeReg(302,0x00000010) lmk.writeReg(303,0x00000041) lmk.writeReg(300,0x00000020) lmk.writeReg(256,0x0000000C) lmk.writeReg(256,0x0000000C) lmk.writeReg(304,0x0000001E) lmk.writeReg(305,0x00000055) lmk.writeReg(307,0x00000000) lmk.writeReg(308,0x00000020) lmk.writeReg(309,0x00000000) lmk.writeReg(310,0x000000F1) lmk.writeReg(311,0x00000001) lmk.writeReg(312,0x00000020) lmk.writeReg(313,0x00000003) lmk.writeReg(314,0x00000001) lmk.writeReg(315,0x00000080) lmk.writeReg(316,0x00000000) lmk.writeReg(317,0x00000008) lmk.writeReg(318,0x00000003) lmk.writeReg(319,0x00000000) lmk.writeReg(320,0x00000000) lmk.writeReg(321,0x00000000) lmk.writeReg(322,0x00000000) lmk.writeReg(323,0x00000012) lmk.writeReg(324,0x000000FF) lmk.writeReg(325,0x00000000) lmk.writeReg(326,0x00000010) lmk.writeReg(327,0x0000001A) lmk.writeReg(328,0x00000002) lmk.writeReg(329,0x00000042) lmk.writeReg(331,0x00000016) lmk.writeReg(332,0x00000000) lmk.writeReg(333,0x00000000) lmk.writeReg(334,0x000000C0) lmk.writeReg(335,0x0000007F) lmk.writeReg(336,0x00000043) lmk.writeReg(337,0x00000002) lmk.writeReg(338,0x00000000) lmk.writeReg(339,0x00000000) lmk.writeReg(340,0x00000078) lmk.writeReg(341,0x00000000) lmk.writeReg(342,0x0000007D) lmk.writeReg(343,0x00000000) lmk.writeReg(344,0x00000096) lmk.writeReg(345,0x00000006) lmk.writeReg(346,0x00000000) lmk.writeReg(347,0x000000D4) lmk.writeReg(348,0x00000020) lmk.writeReg(349,0x00000000) lmk.writeReg(350,0x00000000) lmk.writeReg(351,0x0000000B) lmk.writeReg(352,0x00000000) lmk.writeReg(353,0x00000001) lmk.writeReg(354,0x00000044) lmk.writeReg(355,0x00000000) lmk.writeReg(356,0x00000000) lmk.writeReg(357,0x0000000C) lmk.writeReg(358,0x00000000) lmk.writeReg(359,0x00000000) lmk.writeReg(360,0x0000000C) lmk.writeReg(361,0x00000059) lmk.writeReg(362,0x00000020) lmk.writeReg(363,0x00000000) lmk.writeReg(364,0x00000000) lmk.writeReg(365,0x00000000) lmk.writeReg(366,0x00000013) lmk.writeReg(380,0x00000015) lmk.writeReg(381,0x0000000F) Fuse farm load autoload done successful No autload error Purge Purge MACRO_READY: True MACRO_ACK: True MACRO_DONE: True MACRO_ERROR: False Purge MACRO_READY: True MACRO_ACK: True MACRO_DONE: True MACRO_ERROR: False MACRO_READY: True MACRO_ACK: True MACRO_DONE: True MACRO_ERROR: False SPIA has got control of PLL pages pll0: True; LO Frequency: 3500.01 pll1: True; LO Frequency: 2949.12 PLL Pages SPI control relinquished. FB DSA 3.5G Band RX HD3 default settings begins RX HD3 default settings END RX HD3 default dig-corr begins delay(0.01) delay(0.01) RX HD3 default dig-corr ends RX HD3 default settings begins RX HD3 default settings END RX HD3 default dig-corr begins delay(0.01) delay(0.01) RX HD3 default dig-corr ends Purge Purge Purge *TX IQMC Patch Apply* SPIA has got control of PLL pages PLL Pages SPI control relinquished. FW_VERSION=0x11119e MACRO_READY: True MACRO_ACK: True MACRO_DONE: True MACRO_ERROR: False MACRO_READY: True MACRO_ACK: True MACRO_DONE: True MACRO_ERROR: False attack_value: 2899.74593284 decay_value: 1630.64697059 attack_value: 3650.5638426 decay_value: 1028.86868235 attack_value: 2899.74593284 decay_value: 1630.64697059 attack_value: 3650.5638426 decay_value: 1028.86868235 SPIA has got control of PLL pages PLL Pages SPI control relinquished. Sysref to RX AB, Read: 3; expected: 3 Sysref to RX CD, Read: 3; expected: 3 Sysref to FB A, Read: 1; expected: 1 Sysref to FB D, Read: 1; expected: 1 Sysref to TX AB, Read: 255; expected: 7 Sysref to TX CD, Read: 255; expected: 7 Digital Clock, Read: True; expected: 1 Sysref to Digital, Read: True; expected: 1 Sysref to Analog, Read: 65535; expected: 7 ###########Device DAC JESD-RX 0 Link Status########### LOS Indicator for (Serdes Loss of signal) lane 0: 1 Frame Sync error (unexpected k28.5) for lane 0: 1 LOS Indicator for (Serdes Loss of signal) lane 1: 1 Frame Sync error (unexpected k28.5) for lane 1: 1 LOS Indicator for (Serdes Loss of signal) lane 2: 1 Frame Sync error (unexpected k28.5) for lane 2: 1 LOS Indicator for (Serdes Loss of signal) lane 3: 1 Frame Sync error (unexpected k28.5) for lane 3: 1 lane0 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); lane1 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); lane2 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); lane3 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); lane0 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; lane1 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; lane2 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; lane3 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; CS State TX0: 0b11111111 . It is expected to be 0b00001010 FS State TX0: 0b11111111 . It is expected to be 0b00000101 Couldn't get the link up for device RX: 0; Alarms: 0xfffffffffffffff7L ################################### ###########Device DAC JESD-RX 1 Link Status########### LOS Indicator for (Serdes Loss of signal) lane 0: 1 Frame Sync error (unexpected k28.5) for lane 0: 1 LOS Indicator for (Serdes Loss of signal) lane 1: 1 Frame Sync error (unexpected k28.5) for lane 1: 1 LOS Indicator for (Serdes Loss of signal) lane 2: 1 Frame Sync error (unexpected k28.5) for lane 2: 1 LOS Indicator for (Serdes Loss of signal) lane 3: 1 Frame Sync error (unexpected k28.5) for lane 3: 1 lane0 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); lane1 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); lane2 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); lane3 FIFO Errors=0b1111; Got errors: read_empty : FIFO is empty; read_error : High if read request with empty FIFO (NOTE: only released when JESD block is initialized with init_state); write_full : FIFO is FULL; write_error : High if write request and FIFO is full (NOTE: only released when JESD block is initialized with init_state); lane0 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; lane1 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; lane2 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; lane3 Errors=0b11111111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values; elastic buffer overflow (bad RBD value); link configuration error; frame alignment error; multiframe alignment error; CS State TX0: 0b11111111 . It is expected to be 0b00001010 FS State TX0: 0b11111111 . It is expected to be 0b00000101 Couldn't get the link up for device RX: 1; Alarms: 0xfffffffffffffff7L ################################### SPIA has got control of PLL pages PLL Pages SPI control relinquished. #Done executing .. AFE77xx/bringup/basicBringup_Case-1.py #End Time 2020-10-19 18:30:11.274000 #Execution Time = 446.044999838 s #================ ERRORS:37, WARNINGS:8 ================#
