Hi,
I'm trying to collect adc data from 6843aop using mmwavestudio. All previous steps seems to pass before the dca reports no lvds data. attached is the output log
```
Wed Jun 23 14:48:14 2021
Start Record Command (req)
Wed Jun 23 14:48:14 2021
Start Record command : Success
Wed Jun 23 14:48:14 2021
Return status : 0
Wed Jun 23 14:49:34 2021
Record Process :
Timeout Error! System disconnected
Wed Jun 23 14:49:34 2021
Record stop is done successfully
Wed Jun 23 14:50:33 2021
Start Record Command (req)
Wed Jun 23 14:50:33 2021
Start Record command : Success
Wed Jun 23 14:50:33 2021
Return status : 0
Wed Jun 23 14:51:53 2021
Record Process :
Timeout Error! System disconnected
Wed Jun 23 14:51:53 2021
Record stop is done successfully
Wed Jun 23 14:57:31 2021
Start Record Command (req)
Wed Jun 23 14:57:31 2021
Start Record command : Success
Wed Jun 23 14:57:31 2021
Return status : 0
Wed Jun 23 14:58:51 2021
Record Process :
Timeout Error! System disconnected
Wed Jun 23 14:58:51 2021
Record stop is done successfully
Wed Jun 23 15:02:16 2021
Read DLL Verison Command (req)
Wed Jun 23 15:02:16 2021
DLL Version : 1.0
Wed Jun 23 15:02:18 2021
FPGA Configuration Command (req)
Wed Jun 23 15:02:18 2021
FPGA Configuration :
OS error - -2
Wed Jun 23 15:02:18 2021
Return status : -2
Wed Jun 23 15:02:18 2021
Configure Record Command (req)
Wed Jun 23 15:02:18 2021
Configure Record :
OS error - -2
Wed Jun 23 15:02:18 2021
Return status : -2
Wed Jun 23 15:02:18 2021
Read FPGA version Command (req)
Wed Jun 23 15:02:18 2021
FPGA Version : 0.0 [Record]
Wed Jun 23 15:07:38 2021
Read DLL Verison Command (req)
Wed Jun 23 15:07:38 2021
DLL Version : 1.0
Wed Jun 23 15:07:39 2021
FPGA Configuration Command (req)
Wed Jun 23 15:07:39 2021
FPGA Configuration command : Success
Wed Jun 23 15:07:39 2021
Return status : 0
Wed Jun 23 15:07:39 2021
Configure Record Command (req)
Wed Jun 23 15:07:39 2021
Configure Record command : Success
Wed Jun 23 15:07:39 2021
Return status : 0
Wed Jun 23 15:07:40 2021
Read FPGA version Command (req)
Wed Jun 23 15:07:40 2021
FPGA Version : 2.7 [Record]
Wed Jun 23 15:07:42 2021
Reset FPGA Command (req)
Wed Jun 23 15:07:42 2021
Reset FPGA command : Success
Wed Jun 23 15:07:42 2021
Return status : 0
Wed Jun 23 15:07:43 2021
FPGA Configuration Command (req)
Wed Jun 23 15:07:43 2021
FPGA Configuration command : Success
Wed Jun 23 15:07:43 2021
Return status : 0
Wed Jun 23 15:07:43 2021
Configure Record Command (req)
Wed Jun 23 15:07:43 2021
Configure Record command : Success
Wed Jun 23 15:07:43 2021
Return status : 0
Wed Jun 23 15:07:43 2021
Read FPGA version Command (req)
Wed Jun 23 15:07:43 2021
FPGA Version : 2.7 [Record]
Wed Jun 23 15:07:45 2021
Start Record Command (req)
Wed Jun 23 15:07:45 2021
Start Record command : Success
Wed Jun 23 15:07:45 2021
Return status : 0
Wed Jun 23 15:08:12 2021
Read DLL Verison Command (req)
Wed Jun 23 15:08:12 2021
DLL Version : 1.0
Wed Jun 23 15:08:15 2021
No LVDS data
Wed Jun 23 15:08:15 2021
Record stop is done successfully
Wed Jun 23 15:08:23 2021
Reset FPGA Command (req)
Wed Jun 23 15:08:23 2021
Reset FPGA command : Success
Wed Jun 23 15:08:23 2021
Return status : 0
Wed Jun 23 15:08:23 2021
FPGA Configuration Command (req)
Wed Jun 23 15:08:23 2021
FPGA Configuration command : Success
Wed Jun 23 15:08:23 2021
Return status : 0
Wed Jun 23 15:08:23 2021
Configure Record Command (req)
Wed Jun 23 15:08:23 2021
Configure Record command : Success
Wed Jun 23 15:08:23 2021
Return status : 0
Wed Jun 23 15:08:23 2021
Read FPGA version Command (req)
Wed Jun 23 15:08:23 2021
FPGA Version : 2.7 [Record]
Wed Jun 23 15:08:54 2021
Read DLL Verison Command (req)
Wed Jun 23 15:08:54 2021
DLL Version : 1.0
Wed Jun 23 15:13:19 2021
Read DLL Verison Command (req)
Wed Jun 23 15:13:19 2021
DLL Version : 1.0
Wed Jun 23 15:13:22 2021
FPGA Configuration Command (req)
Wed Jun 23 15:13:22 2021
FPGA Configuration command : Success
Wed Jun 23 15:13:22 2021
Return status : 0
Wed Jun 23 15:13:22 2021
Configure Record Command (req)
Wed Jun 23 15:13:22 2021
Configure Record command : Success
Wed Jun 23 15:13:22 2021
Return status : 0
Wed Jun 23 15:13:23 2021
Read FPGA version Command (req)
Wed Jun 23 15:13:23 2021
FPGA Version : 2.7 [Record]
Wed Jun 23 15:14:51 2021
Start Record Command (req)
Wed Jun 23 15:14:51 2021
Start Record command : Success
Wed Jun 23 15:14:51 2021
Return status : 0
Wed Jun 23 15:15:21 2021
No LVDS data
Wed Jun 23 15:15:21 2021
Record stop is done successfully
Wed Jun 23 15:15:38 2021
Start Record Command (req)
Wed Jun 23 15:15:38 2021
Start Record command : Success
Wed Jun 23 15:15:38 2021
Return status : 0
Wed Jun 23 15:15:40 2021
Read DLL Verison Command (req)
Wed Jun 23 15:15:40 2021
DLL Version : 1.0
Wed Jun 23 15:15:43 2021
reset_fpga
Wed Jun 23 15:15:43 2021
Stop the already running process.
Wed Jun 23 15:15:43 2021
fpga
Wed Jun 23 15:15:43 2021
Stop the already running process.
Wed Jun 23 15:15:43 2021
record
Wed Jun 23 15:15:43 2021
Stop the already running process.
Wed Jun 23 15:15:43 2021
fpga_version
Wed Jun 23 15:15:43 2021
Stop the already running process.
Wed Jun 23 15:15:52 2021
fpga
Wed Jun 23 15:15:52 2021
Stop the already running process.
Wed Jun 23 15:15:52 2021
record
Wed Jun 23 15:15:52 2021
Stop the already running process.
Wed Jun 23 15:15:52 2021
fpga_version
Wed Jun 23 15:15:52 2021
Stop the already running process.
Wed Jun 23 15:16:08 2021
No LVDS data
Wed Jun 23 15:16:08 2021
Record stop is done successfully
Wed Jun 23 15:16:17 2021
FPGA Configuration Command (req)
Wed Jun 23 15:16:17 2021
FPGA Configuration command : Success
Wed Jun 23 15:16:17 2021
Return status : 0
Wed Jun 23 15:16:17 2021
Configure Record Command (req)
Wed Jun 23 15:16:17 2021
Configure Record command : Success
Wed Jun 23 15:16:17 2021
Return status : 0
Wed Jun 23 15:16:18 2021
Read FPGA version Command (req)
Wed Jun 23 15:16:18 2021
FPGA Version : 2.7 [Record]
Wed Jun 23 15:16:19 2021
Reset FPGA Command (req)
Wed Jun 23 15:16:19 2021
Reset FPGA command : Success
Wed Jun 23 15:16:19 2021
Return status : 0
Wed Jun 23 15:16:19 2021
FPGA Configuration Command (req)
Wed Jun 23 15:16:19 2021
FPGA Configuration command : Success
Wed Jun 23 15:16:19 2021
Return status : 0
Wed Jun 23 15:16:19 2021
Configure Record Command (req)
Wed Jun 23 15:16:19 2021
Configure Record command : Success
Wed Jun 23 15:16:19 2021
Return status : 0
Wed Jun 23 15:16:20 2021
Read FPGA version Command (req)
Wed Jun 23 15:16:20 2021
FPGA Version : 2.7 [Record]
Wed Jun 23 15:16:21 2021
FPGA Configuration Command (req)
Wed Jun 23 15:16:21 2021
FPGA Configuration command : Success
Wed Jun 23 15:16:21 2021
Return status : 0
Wed Jun 23 15:16:21 2021
Configure Record Command (req)
Wed Jun 23 15:16:21 2021
Configure Record command : Success
Wed Jun 23 15:16:21 2021
Return status : 0
Wed Jun 23 15:16:21 2021
Read FPGA version Command (req)
Wed Jun 23 15:16:21 2021
FPGA Version : 2.7 [Record]
Wed Jun 23 15:16:29 2021
Start Record Command (req)
Wed Jun 23 15:16:29 2021
Start Record command : Success
Wed Jun 23 15:16:29 2021
Return status : 0
Wed Jun 23 15:16:59 2021
No LVDS data
Wed Jun 23 15:16:59 2021
Record stop is done successfully
Wed Jun 23 15:17:32 2021
Start Record Command (req)
Wed Jun 23 15:17:32 2021
Start Record command : Success
Wed Jun 23 15:17:32 2021
Return status : 0
Wed Jun 23 15:18:02 2021
No LVDS data
Wed Jun 23 15:18:02 2021
Record stop is done successfully
Wed Jun 23 15:20:53 2021
Start Record Command (req)
Wed Jun 23 15:21:03 2021
Start Record :
Timeout Error! System disconnected
Wed Jun 23 15:21:03 2021
Return status : -5
Wed Jun 23 15:21:07 2021
Start Record Command (req)
Wed Jun 23 15:21:07 2021
Start Record command : Success
Wed Jun 23 15:21:07 2021
Return status : 0
Wed Jun 23 15:21:09 2021
Read DLL Verison Command (req)
Wed Jun 23 15:21:09 2021
DLL Version : 1.0
Wed Jun 23 15:21:23 2021
No LVDS data
Wed Jun 23 15:21:23 2021
Record stop is done successfully
Wed Jun 23 15:23:24 2021
Start Record Command (req)
Wed Jun 23 15:23:24 2021
Start Record command : Success
Wed Jun 23 15:23:24 2021
Return status : 0
Wed Jun 23 15:23:54 2021
No LVDS data
Wed Jun 23 15:23:54 2021
Record stop is done successfully
Wed Jun 23 15:24:17 2021
Start Record Command (req)
Wed Jun 23 15:24:17 2021
Start Record command : Success
Wed Jun 23 15:24:17 2021
Return status : 0
Wed Jun 23 15:24:47 2021
No LVDS data
Wed Jun 23 15:24:47 2021
Record stop is done successfully
Wed Jun 23 15:25:07 2021
Start Record Command (req)
Wed Jun 23 15:25:07 2021
Start Record command : Success
Wed Jun 23 15:25:07 2021
Return status : 0
Wed Jun 23 15:25:37 2021
No LVDS data
Wed Jun 23 15:25:37 2021
Record stop is done successfully
Wed Jun 23 15:27:03 2021
Start Record Command (req)
Wed Jun 23 15:27:03 2021
Start Record command : Success
Wed Jun 23 15:27:03 2021
Return status : 0
Wed Jun 23 15:27:32 2021
No LVDS data
Wed Jun 23 15:27:32 2021
No Header
Wed Jun 23 15:27:32 2021
Record stop is done successfully
Wed Jun 23 15:27:43 2021
Read DLL Verison Command (req)
Wed Jun 23 15:27:43 2021
DLL Version : 1.0
Wed Jun 23 15:27:46 2021
FPGA Configuration Command (req)
Wed Jun 23 15:27:46 2021
FPGA Configuration command : Success
Wed Jun 23 15:27:46 2021
Return status : 0
Wed Jun 23 15:27:46 2021
Configure Record Command (req)
Wed Jun 23 15:27:46 2021
Configure Record command : Success
Wed Jun 23 15:27:46 2021
Return status : 0
Wed Jun 23 15:27:46 2021
Read FPGA version Command (req)
Wed Jun 23 15:27:46 2021
FPGA Version : 2.7 [Record]
Wed Jun 23 15:27:51 2021
Start Record Command (req)
Wed Jun 23 15:27:51 2021
Start Record command : Success
Wed Jun 23 15:27:51 2021
Return status : 0
Wed Jun 23 15:28:21 2021
No LVDS data
Wed Jun 23 15:28:21 2021
Record stop is done successfully
Wed Jun 23 15:34:17 2021
Read DLL Verison Command (req)
Wed Jun 23 15:34:17 2021
DLL Version : 1.0
Wed Jun 23 15:35:48 2021
Start Record Command (req)
Wed Jun 23 15:35:48 2021
Start Record command : Success
Wed Jun 23 15:35:48 2021
Return status : 0
Wed Jun 23 15:36:18 2021
No LVDS data
Wed Jun 23 15:36:18 2021
Record stop is done successfully
Wed Jun 23 16:16:27 2021
Read DLL Verison Command (req)
Wed Jun 23 16:16:27 2021
DLL Version : 1.0
Wed Jun 23 16:16:30 2021
FPGA Configuration Command (req)
Wed Jun 23 16:16:30 2021
FPGA Configuration command : Success
Wed Jun 23 16:16:30 2021
Return status : 0
Wed Jun 23 16:16:30 2021
Configure Record Command (req)
Wed Jun 23 16:16:30 2021
Configure Record command : Success
Wed Jun 23 16:16:30 2021
Return status : 0
Wed Jun 23 16:16:30 2021
Read FPGA version Command (req)
Wed Jun 23 16:16:30 2021
FPGA Version : 2.8 [Record]
Wed Jun 23 16:17:31 2021
Start Record Command (req)
Wed Jun 23 16:17:31 2021
Start Record command : Success
Wed Jun 23 16:17:31 2021
Return status : 0
Wed Jun 23 16:18:01 2021
No LVDS data
Wed Jun 23 16:18:01 2021
Record stop is done successfully
Wed Jun 23 16:30:07 2021
Start Record Command (req)
Wed Jun 23 16:30:07 2021
Start Record Command (req)
Wed Jun 23 16:30:07 2021
Start Record command : Success
Wed Jun 23 16:30:07 2021
Return status : 0
Wed Jun 23 16:30:07 2021
Start Record command : Success
Wed Jun 23 16:30:37 2021
No LVDS data
Wed Jun 23 16:30:37 2021
Record stop is done successfully
Wed Jun 23 16:52:52 2021
Read DLL Verison Command (req)
Wed Jun 23 16:52:53 2021
DLL Version : 1.0
Wed Jun 23 16:52:54 2021
FPGA Configuration Command (req)
Wed Jun 23 16:53:04 2021
FPGA Configuration :
Timeout Error! System disconnected
Wed Jun 23 16:53:04 2021
Return status : -5
Wed Jun 23 16:53:04 2021
Configure Record Command (req)
Wed Jun 23 16:53:12 2021
Ethernet connection
Wed Jun 23 16:53:12 2021
Ethernet connection failed. [error -4051]
Wed Jun 23 16:53:12 2021
Ethernet connection
Wed Jun 23 16:53:12 2021
Ethernet connection failed. [error -4051]
Wed Jun 23 16:53:13 2021
Ethernet connection
Wed Jun 23 16:53:13 2021
Ethernet connection failed. [error -4051]
Wed Jun 23 16:53:14 2021
Configure Record :
Timeout Error! System disconnected
Wed Jun 23 16:53:14 2021
Return status : -5
Wed Jun 23 16:53:15 2021
FPGA Configuration Command (req)
Wed Jun 23 16:53:15 2021
FPGA Configuration command : Success
Wed Jun 23 16:53:15 2021
Return status : 0
Wed Jun 23 16:53:15 2021
Read FPGA version Command (req)
Wed Jun 23 16:53:15 2021
FPGA Version : 2.8 [Record]
Wed Jun 23 16:53:15 2021
Configure Record Command (req)
Wed Jun 23 16:53:15 2021
Configure Record command : Success
Wed Jun 23 16:53:15 2021
Return status : 0
Wed Jun 23 16:53:15 2021
Read FPGA version Command (req)
Wed Jun 23 16:53:15 2021
FPGA Version : 2.8 [Record]
Wed Jun 23 16:53:17 2021
FPGA Configuration Command (req)
Wed Jun 23 16:53:17 2021
FPGA Configuration command : Success
Wed Jun 23 16:53:17 2021
Return status : 0
Wed Jun 23 16:53:18 2021
Configure Record Command (req)
Wed Jun 23 16:53:18 2021
Configure Record command : Success
Wed Jun 23 16:53:18 2021
Return status : 0
Wed Jun 23 16:53:18 2021
Read FPGA version Command (req)
Wed Jun 23 16:53:18 2021
FPGA Version : 2.8 [Record]
Wed Jun 23 16:56:37 2021
Read DLL Verison Command (req)
Wed Jun 23 16:56:37 2021
DLL Version : 1.0
Wed Jun 23 16:56:39 2021
FPGA Configuration Command (req)
Wed Jun 23 16:56:39 2021
FPGA Configuration command : Success
Wed Jun 23 16:56:39 2021
Return status : 0
Wed Jun 23 16:56:39 2021
Configure Record Command (req)
Wed Jun 23 16:56:39 2021
Configure Record command : Success
Wed Jun 23 16:56:39 2021
Return status : 0
Wed Jun 23 16:56:39 2021
Read FPGA version Command (req)
Wed Jun 23 16:56:39 2021
FPGA Version : 2.8 [Record]
Wed Jun 23 20:01:59 2021
Read DLL Verison Command (req)
Wed Jun 23 20:01:59 2021
DLL Version : 1.0
Wed Jun 23 20:02:01 2021
FPGA Configuration Command (req)
Wed Jun 23 20:02:01 2021
FPGA Configuration command : Success
Wed Jun 23 20:02:01 2021
Return status : 0
Wed Jun 23 20:02:01 2021
Configure Record Command (req)
Wed Jun 23 20:02:01 2021
Configure Record command : Success
Wed Jun 23 20:02:01 2021
Return status : 0
Wed Jun 23 20:02:01 2021
Read FPGA version Command (req)
Wed Jun 23 20:02:01 2021
FPGA Version : 2.8 [Record]
Wed Jun 23 21:00:46 2021
Start Record Command (req)
Wed Jun 23 21:00:56 2021
System is disconnected.
Wed Jun 23 21:00:56 2021
Return status : -5
Wed Jun 23 21:01:00 2021
Start Record Command (req)
Wed Jun 23 21:01:00 2021
Start Record Command (req)
Wed Jun 23 21:01:01 2021
Start Record command : Success
Wed Jun 23 21:01:01 2021
Return status : 0
Wed Jun 23 21:01:01 2021
Start Record command : Success
Wed Jun 23 21:01:30 2021
No LVDS data
Wed Jun 23 21:01:30 2021
No Header
Wed Jun 23 21:01:30 2021
Record stop is done successfully
Wed Jun 23 21:03:59 2021
Start Record Command (req)
Wed Jun 23 21:03:59 2021
Start Record Command (req)
Wed Jun 23 21:04:00 2021
Start Record command : Success
Wed Jun 23 21:04:00 2021
Return status : 0
Wed Jun 23 21:04:00 2021
Start Record command : Success
Wed Jun 23 21:04:29 2021
No LVDS data
Wed Jun 23 21:04:29 2021
No Header
Wed Jun 23 21:04:29 2021
Record stop is done successfully
```
