AMC80: The I2C communication of AMC80

Hi Lacey,

Some comments:
Based on the A0-A2 pins tied to ground, the oscilloscope picture shows the correct I2C address (0101000) was sent. Since these pins are input-only, a smaller resistor could be used, and may provide a more reliable ground level for the device to detect.

SDA is a bidirectional signal. The CPLD host must transition to high impedance (noted as Z in HDL) to allow the AMC80 slave to respond. Please ensure your CPLD IO for SDA is configured to operate this way. This type of operation is also known as Open-Drain.

Your communication occurs about 1ms after the I2C lines power on. If the AMC80 is being powered on at the same time, it may not be ready to respond at this time. Could you try communicating with the AMC80 100ms or even 1s after the power on event?

Thanks,
Ren

Lacey -
Also, if I may jump in here and add to Ren's comments - do you have pull up resistors on your SCL and SDA lines? I don't see them in the drawing you posted.

Page 4 of the DS, here ==> www.ti.com/.../amc80.pdf has table which states pull up resistors are needed. (this is always the case on I2C) and if you are missing those, it would be good to start there and add them -
On the reference design (EVM), 4.02k Ohm resistors were used (Stackpole PN RMCF0603FT4K02) and you can see this application note on the topic of calculating the value needed, based on your board layout and operating voltage. www.ti.com/.../slva689.pdf

Hello Lacey,

Additionally to the points already raised

1. The schematic shows a LM96080 and not an AMC80. Are you sure the customer is using LM96080 and not a AMC80 (though they are pin compatible device). Can you please confirm the same?
2. How long is the RST from the CPLD to the FAN Controller and after Reset is de-asserted, how long after that is the I2C communication started. If you can get a scope shot for the timing of the RST to I2C access, that would be useful as well.
3. Lastly, can the customer check the state of the pins when the device is not responding and no active access is occurring?

Hi Ashara and Ren,

Thanks so much for your help!

1. Because customer are planning to do the p2p replacement for LM96080 using the AMC80, so the name in schematic is still LM96080.

2. They have the pull up resistor, the value is 4.7k, as below:

3. They also check the CPLD status is correct.

4. After power up the device, the CPLD will reset the AMC80. The communication is done in 8.4us after CPLD reset the AMC80.

   In addition, they increase the 8.4us to 310us, the communication is still failure.

Lacey

Thanks a lot!

Hello Lcaey,

The first transaction seems to have been ACK'ed. Looking back at the datasheet for AMC80, it suggests doing a 2 byte write and read. Can you try the same and then let us know if the 2nd transaction works?

Can you help to explain more about the 2nd transaction?

Customer said they still can't do normal communication by I2C interface.

Lacey

Thanks a lot!

Hello Lacey,

In the first scope shot, the transaction to write to the register 0x0 is ACK'ed by the slave. The 2nd transaction is in the 2nd scope shot which has a NAK.

Hi Ashara,
The communication stop in the second transaction.
Now it's hard to find the cause for not ACK.
So the p2p replacement test is pending.

Can you help to suggest the test for this debug?


Lacey
Thanks a lot!

Hello Lacey,

Can the customer try to add some delay between the two transactions and then check?

Hi Ashara,
you mean the 310us is also not enough?
Lacey
Thanks a lot!

Hi Ashara,
For the detail test results, I will reach you via email.
Thanks a lot