We are seeing unexpected behavior on the TMP431. The following document was used for functionality description: SBOS441H –SEPTEMBER 2009–REVISED MARCH 2016
There are two separate issues, as follows:
1) Every access to the SMBus alarm response address will set the MASK bit in register 0x3/0x9. The scenario is this: device hits one of the alarm limits, ALARM is asserted. The condition then goes away. An SMBus ARA is issued to dessert ALARM. As soon as the TMP431 receives the ARA, it internally sets MASK in the config register 0x3/0x9 thus no interrupt will ever occur form this device, until the mask is cleared.
Comment - Since there is no mention of this behavior in the above referenced document, we consider this a bug.
2) The above referenced document states: “Clearing the Status Register bits does not clear the state of the ALERT pin; an SMBus alert response address command must be used to clear the ALERT pin.”
Comment - This statement is demonstrably false. Provided the condition that triggered the alarm has gone away, a simple read of the status register clears not only the status register bits, but deserts the ALARM signal, in direct contradiction with the quote above.