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Hello,
I was wondering if we could get the load characteristics, as well as the expected frequency, wave type, and peak to peak voltage for the SYNC_OUT signal in a cascaded design with more than 2 slave chips. I am not able to find this in the AWR2243 or AWR2243 Cascade datasheets.
Thanks,
Robert
Hi Robert,
Do you mean the FMCW_SYNCOUT/CLKOUT LO signals? or the DIG_SYNCOUT signals?
Thank you,
-Randy
Hi Randy,
I'm looking at the Digital SYNCOUT signals, which as I understand it, is different than the 40 MHz OSC_CLKOUT. It is shown as "SYNC_OUT and SYNC_IN" in figure 1 of the AWR2243 Cascade Application Report.
Robert
Hi Robert,
Syncout (P11) is a GND to VDDIO LVCMOS signal. Based on frame timing, this signal will provide ~6ns wide low-high-low pulse for the slaved cascade devices or other external equipment to synchronize to.
The VOH/VOL numbers in the datasheet reference all of the digital IO on the VIOIN power net including the Syncout pin. So the IOH = 6mA is applicable. In the case of our MMWCAS-RF-EVM we are driving a LMK00804B clock buffer CLK input with Syncout. The LMK00804B datasheet shows the receiver loading for CLK to be 51kohm.
Thank you,
-Randy