This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN74CBTLV3253: Can the switch selection pins(S0 & S1) be left floating

Part Number: SN74CBTLV3253

Hi, 

On one our boards, we are using this switch to multiplex a logic signal. I had a question here. Can we float one of the selection pin (S1)? 

I do not have the use of lower two channels (1B3 & 1B4), so I am just using S0 to switch between 1A-1B1 & 1A-1B2. I could not find input impedance of selection gates on the datasheet. I know recommendations would be to pull S1 low, but I already have a board which needs a fix. So question is, how much would the input impedance on S1 be, to see if that can be left floating with any degree of confidence?

Thanks,

AQ

  • The input impedance can be deduced from II.

    Anyway, the control input must not float; see footnote (1) in section 6.3. You can connect the pin directly to VCC or GND.

  • Hi AQ,

    The logic inputs, such as Select pins, OE pins, and other logic inputs, should never be left floating. They should  be, by default, tied to either VCC or GND

    This FAQ covers your question on what to do with unused inputs/outputs of a switch:

    The impedance of a device's pin can be determined by Ohm's law : R= V/ I. It is mostly very high for CMOS input pins (SEL, OE, A, B)

    the Electrical spec lists the input leakage max of 1uA (for Vcc of 3.6V) on the input pins. The R can be estimated by R = 3.6V / 1uA = 3.6 Mohm. 

    Regards,

    Saminah

  • Thanks Saminah for the reply. Appreciate it. 

    AQ