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Part Number: CD4051B
I have some questions about the input threshold.
My customer uses VDD=5V, but the input voltage reaches 6.3V due to inappropriate resistors. After several tests, our device is broken. I think the root cause is that the input exceeds VDD+0.5V, because we request that '' input should not be pushed than 0.5V above VDD'' in the datasheet. But I don't know why the chip is broken when the input is 6.3V (VDD=5V). The signal pin's maximum rating should be larger than 6.3V. Because if the VDD=12V, the input can be up to 12.5V. Could you please help explain why the input is limited by VDD? When the input exceeds VDD+0.5, how is our device damaged?
Thanks & Best Regards,
You can see in the abs max table that if a voltage on the signal path is greater than VDD +0.5V, then the internal ESD diodes get forward-biased. You can expect a high-current drawn from the input source into the supply voltage VDD/VSS of the multiplexer. If this current exceeds the absolute maximum rating of the internal ESD diodes (10m A in this case), then the multiplexer internal ESD structure can fail, leading to device failure
As you can see, the 6.3V on the I/O pin is exceeding the VDD + 0.5 limit - please refer to the Note (1) below the Absolute maximum ratings table for more details.
You can use internal ESD diode to clamp the voltage as long as you maintain the current limits. This is a concept many customers implement in their systems. Here is a good link to show how to use the internal diode, or an external diode to clamp the voltage, or use a series resistor to limit the current.
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In reply to Saminah C:
Got it! Thanks for your help!
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