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CODECOMPOSER: [tda4vl][c7x]: CCS cached DDR memory Identification

Karthick Raja Panchapakesan
Intellectual 821 points
Part Number: CODECOMPOSER
Other Parts Discussed in Thread: TDA4VM

Tool/software:

Hi TI Team,

Is there a way to identify in CCS when using debugger that a particular region of DDR is cached or not. 

We except like if we go to memory browser the cached DDR region shall be shown in different colour.

regards,

Karthick

  • 0
    TI__Guru**** 450031 points

    Hello,

    Karthick Raja Panchapakesan said:
    We except like if we go to memory browser the cached DDR region shall be shown in different colour.

    We do have that feature in the Memory Browser view. The below is an image of the CCS 12.8.0 Memory Browser for the C71x of my TDA4VM:

    Do you not see this functionality in your environment?

    Thanks

    ki

  • 0 in reply to Ki
    Intellectual 821 points

    Hi Ki,

    We are using CCS V12.4 and we don't see Color differences.

    The DDR region 0xBB800000 + 2MB is made cacheable in c7x2 -> appInit.c ->  attrs.attrIndx = Mmu_AttrIndx_MAIR7; -> under this section we have added the memory region 0xBB800000 + 2MB.

    regards,

    Karthick

  • 0 in reply to Karthick Raja Panchapakesan
    TI__Guru**** 450031 points

    You would only see the color highlighting if there was something at that address was actually cached. Otherwise it will appear as you see it.

  • 0 in reply to Ki
    Intellectual 821 points

    Hi Ki,

    That's what I am caching 2MB memory region in DDR, but it is not reflecting.

    Even for other cores like R5F I am not able to see any color change at all. All are in white, we are sure many regions are cached in R5F atleast, but the entire DDR region is in white color for us. Please let us know if we are missing any setting.

    //karthick

  • 0 in reply to Karthick Raja Panchapakesan
    TI__Intellectual 1260 points

    Do you have program or data in the DDR? If data, can you confirm that you enabled data cache in addition to making the region cacheable? Can you try executing code from DDR and see if that shows as cached in the Memory Browser?