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Error -1029 @ 0x2B5F when changing ARM926 clock

Paul Singh
Expert 2750 points
Other Parts Discussed in Thread: OMAPL138

Hello CCS experts,

An error has been found when trying to set L138 ARM core into wait-for-interrupt sleep mode with the following ccs 5.1.1.00031 console message:
ARM9_0: Error: (Error -1029 @ 0x2B5F) Invalid data read from ICECrusher register. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.569.0)  

 
          
C code below, modified on the basis of evmomapl138 initialization gel, is used to set ARM core’s PSC to “disable”,
   
/*PSC Module Related Registers*/
#define PSC0_BASE       0x01C10000
#define PSC1_BASE       0x01E27000
 
#define PSC0_MDCTL      (PSC0_BASE+0xA00)
#define PSC0_MDSTAT     (PSC0_BASE+0x800)
#define PSC0_PTCMD      *(unsigned int*) (PSC0_BASE + 0x120)
#define PSC0_PTSTAT     *(unsigned int*) (PSC0_BASE + 0x128)
 
#define PSC_TIMEOUT      200
 
void PSC0_LPSC_disable(unsigned int PD, unsigned int LPSC_num) {
    unsigned int j;
 
    if( (*(unsigned int*)(PSC0_MDSTAT+4 * LPSC_num) & 0x1F) != 0x2 ) {
      *(unsigned int*) (PSC0_MDCTL+4*LPSC_num) = (*(unsigned int*) (PSC0_MDCTL+4*LPSC_num) & 0xFFFFFFE0) | 0x0002; //KT: why clear bit 4-0?
      PSC0_PTCMD = 0x1<<PD;
 
      j = 0;
      /*Wait for power state transition to finish*/
      while( (PSC0_PTSTAT & (0x1<<PD) ) !=0) {
        if( j++ > PSC_TIMEOUT ) {
//          GEL_TextOut("\tPSC0 Enable Transition Timeout on Domain %d, LPSC %d\n","Output",1,1,1,PD,LPSC_num);
          break;
        }
      }
 
      j = 0;
      while( (*(unsigned int*)(PSC0_MDSTAT+4 * LPSC_num) & 0x1F) !=0x2) {
        if( j++ > PSC_TIMEOUT ) {
//          GEL_TextOut("\tPSC0 Enable Verify Timeout on Domain %d, LPSC %d\n","Output",1,1,1,PD,LPSC_num);
          break;
        }
      }
    }
}
     
And such code was invoked on the DSP side using
           
PSC0_LPSC_disable(0,14);
 
On the ARM side, an ISR corresponding to ARMCLKSTOPREQ event has been set, and has been tested to be responsive by manually setting bit 26 (26+64(start index of SRSR3)=90, the interrupt number of ARMCLKSTOPREQ) of AINTC.SRSR3 register and observing that the ISR would be triggered. However, problem arises when trying to completing the process by:

1.    Turning PSC0 ARM module to wait-for-interrupt sleep on the DSP side.

2.    Expect the triggered ARMCLKSTOPREQ ISR on the ARM core to execute the MCR p15, #0, r3, c7, c0, #4 command to put the ARM core into WFI sleep.

As soon as DSP executes PSC0_LPSC_disable(0,14), the error message in red font immediately appears in the console window. The status of the emulator connection to DSP core would be “In reset(secure)”, and the status of ARM connection would be “running”.
 
The error code is “Error -1029 @ 0x2B5F”, and with this string I could found several related threads:

1.    http://e2e.ti.com/support/development_tools/code_composer_studio/f/81/t/104540.aspx#370046, by JohnS, suggesting using adaptive clocking and lower JTAG clock. He also refers to http://processors.wiki.ti.com/index.php/XDS100#Q:_My_XDS100v2_does_not_work_reliabily_with_the_OMAPL138_.2F_DM365_.2F_ARM926_core

2.    http://e2e.ti.com/support/development_tools/code_composer_studio/f/81/p/178069/662011.aspx#662011

3.    http://e2e.ti.com/support/development_tools/code_composer_studio/f/81/p/111531/394883.aspx#394883

4.    http://e2e.ti.com/support/development_tools/code_composer_studio/f/81/t/112716.aspx

5.    http://e2e.ti.com/support/development_tools/code_composer_studio/f/81/t/103398.aspx

   
It seems that the first one is the most pertinent, but it didn’t solve the problem on my machine. I am considering buying a XDS510 USB PLUS emulator but for the time being I am still using a SEED XDS560 PLUS type.
            
Because this error occurs during attempts to change PSC (domain clock on/off) , the most reasonable explanation seems to be at the wiki link JohnS referred to. However I still haven’t been able to solve my problem with the information.
 
Appreciate any help on this.
  
  
Paul
  • 0
    Expert 2750 points

    Also regarding the wiki link JohnS referred:

    The fist of its suggestion is to use code rather than GEL for changing the PLL:

    http://processors.wiki.ti.com/index.php/XDS100#Q:_My_XDS100v2_does_not_work_reliabily_with_the_OMAPL138_.2F_DM365_.2F_ARM926_core said:

    A couple of things to try:

    1. Setup the PLL by executing code (ex: UBoot, etc.) instead of using the GEL file. (preferred)
    2. Turn on adaptive clocking XDS100#Q:_How_can_I_turn_on_adaptive_clocking.3F and setup the timeouts to very slow. In this mode, it is still better to "run" the code and not "step" it.
    3. Make sure you have the latest CPLD version. To update the XDS100v2 CPLD, please see XDS100#Q:_How_can_I_update_the_CPLD_on_my_XDS100v2.3F

    I have tried both code and GEL methods, and the error message when disabling ARM PSC can be seen at the lower half the the screenshot attached above. The error exists regardless of the GEL/code choice.