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Hi
I am new to Code composer studio.
I face difficulty in understanding the memory mapping in linker command file used in ccs project.
Versions info :
CPU : TMS320F28069
CCS: Version: 5.2.1.00018
The PAGE 1 memory layout in the lcf has following details:
PAGE 1:
/* Data Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
/* Registers remain on PAGE1 */
RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
dataRAM : origin = 0x008C00, length = 0x001400
RAML4 : origin = 0x00A000, length = 0x008000 /* on-chip RAM block L4 */
RAML8 : origin = 0x012000, length = 0x002000 /* on-chip RAM block L8 */
}
I read from the datasheet of the device that it has only MO, M1, L0, L1 regions. But the linker command file uses dataRAM, RAML4, RAML8 regions as mentioned above. These regions appears to overlap the reserved memory regions of the device.
May i get some clarification on this?
For information
The final map file shows that these regions are used by the Linker for some of the sections. The code works fine on the board.
Thanks and Regards
Murali K V
Alas !!! i found out.
I was referring to wrong version of the Datasheet -> TMS320F2806 -> which has only M0, M1, L0, L1 regions. !!!
The datasheet for TMS320F28069 has the detailed information on the ram regions L0,L1,L2,L3,L4,L5,L6,L7,L8.
Thanks
Murali K V