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CCS/BEAGLEBOARD-X15: Running two different codes in different cores

chaitanya krishna74
Prodigy 100 points
Part Number: BEAGLEBOARD-X15

Tool/software: Code Composer Studio

Hi ,

I have fallowed the steps mentioned  http://processors.wiki.ti.com/index.php/Multi-Core_Debug_with_CCS . 

I created two different ccs projects with simple printf in each project. Then launched the target configuration and connected targets cortexa15_0 & cortexa15_1 .

Then loaded two different projects in cores and grouped the two cores .

Up to here it is fine but the problem is when run the two cores one core is working and the other one goes to undefined instruction or unhandled adp instruction.

Please help me in this.

Thanks & Regards,

Chaitanya.

  • 0
    TI__Guru**** 169894 points
    Chaitanya,

    One common problem when creating projects for multicore devices is to be sure they are not using the same memory.

    For example, if you are allocating your code to external DDR on both projects, you must separate their memory segments in the linker script file so they do not overlap. Otherwise, you may end up with one core locking up when the other core is running normally and modifying variables, jumping to routines, etc.

    Assuming that your projects are using the pre-installed linker script files, at the top of each AM572x.lds file you will have to modify the entries to separate their memories:

    Core 0:
    MEMORY
    {

    OCMC_RAM1 : o = 0x40300000, l = 0x00080000 /* 512kB L3 OCMC RAM1 */
    OCMC_RAM2 : o = 0x40400000, l = 0x00100000 /* 1MB L3 OCMC RAM2 */
    OCMC_RAM3 : o = 0x40500000, l = 0x00100000 /* 1MB L3 OCMC RAM3 */
    DDR0_0 : o = 0x80000000, l = 0x20000000 /* 512MB external DDR Bank 0 */
    DDR1 _0: o = 0xC0000000, l = 0x20000000 /* 512MB external DDR Bank 1 */

    }

    Core 1:
    MEMORY
    {

    OCMC_RAM1 : o = 0x40300000, l = 0x00080000 /* 512kB L3 OCMC RAM1 */
    OCMC_RAM2 : o = 0x40400000, l = 0x00100000 /* 1MB L3 OCMC RAM2 */
    OCMC_RAM3 : o = 0x40500000, l = 0x00100000 /* 1MB L3 OCMC RAM3 */
    DDR0_1 : o = 0xA0000000, l = 0x20000000 /* 512MB external DDR Bank 0 */
    DDR1_1 : o = 0xE0000000, l = 0x20000000 /* 512MB external DDR Bank 1 */

    }

    On the rest of the file you must replace the DDR0 entries with the corresponding segments above (DDR0_0 or DDR0_1 depending on the core).

    Additional details about memory segments on linker files can be seen at:
    processors.wiki.ti.com/.../Linker_Command_File_Primer

    Hope this helps,
    Rafael
  • 0 in reply to desouza
    Prodigy 100 points

    Hi Rafael,

    Thank you ,this solved my problem . But I have small doubt how interrupts will be directed to core. That is only one core will handle interrupts or both. If only one which core will handle the interrupts. And is there any way to redirect interrupts to other  cores.

    Thanks & Regards,

    Chaitanya.

  • 0 in reply to chaitanya krishna74
    TI__Guru**** 169894 points
    Chaitanya,

    I am not really sure; I suspect the interrupt vector table is unique for both cores (allocated in shared memory) but I am not an expert on the device. This question can be better addressed by the experts on the Sitara forum.

    Regards,
    Rafael