Compiler: how to make code generation with OMAP-L138 Experimenter Kit, CCSv5.5 and MATLAB SIMULINK

Tool/software: TI C/C++ Compiler

Hello, everyone!

Now I am using the model-based design to develop the TMS320C6748, but I have encountered problems during the configuration process, I hope to get everyone's support and help especially Zhirong Liang,

I have set the environment variables ，xmakefilesetup and the model configuration according to the website e2e.ti.com/.../402222 

checkEnvSetup('ccsv5', 'c6748evm', 'check')

1. CCSv5 (Code Composer Studio)
Your version : 5.5.0
Required version: 5.0 or later
Required for : Code Generation
TI_DIR="C:\ti\ccsv5"

2. C6000 CSL (TMS320C6000 Chip Support Library)
Your version : 2.31.00.15
Required version: 2.31.00.10 or later
Required for : Code generation
CSL_C6000_INSTALLDIR="C:\ti\ccsv5\C6xCSL"
CSL_C6000_INSTALLDIR="C:\ti\ccsv5\C6xCSL"

3. XDC Tools (eXpress DSP Components)
Your version : 3.25.04.88
Required version: 3.16.02.32 or later
Required for : Code generation

4. CGT (Code Generation Tools)
Your version : 6.1.23
Required version: 6.1.18 to 7.3.1
Required for : Code generation
C6000_CGT_INSTALLDIR="C:\ti\ccsv5\tools\compiler\C6000"
C6000_CGT_INSTALLDIR="C:\ti\ccsv5\tools\compiler\C6000"

5. DSP/BIOS (Real Time Operating System)
Your version : 5.41.11.38
Required version: 5.33.05 to 5.41.11.38
Required for : Code generation
CCSV5_DSPBIOS_INSTALLDIR="C:\ti\ccsv5\bios_5_41_11_38"
CCSV5_DSPBIOS_INSTALLDIR="C:\ti\ccsv5\bios_5_41_11_38"

6. Texas Instruments IMGLIB (C64x+ Image Library)
Your version : 2.1.0.0
Required version: 2.0.1 or later
Required for : CRL block replacement
C64XP_IMGLIB_INSTALLDIR="C:\ti\ccsv5\c64plus-imglib_2_02_00_00"

7. NDK (NDK 2.00)
Your version : 2.00.00
Required version: 2.00.00 or later
Required for : External mode and Ethernet blocks
NDK_EVMC6748_INSTALLDIR="C:\CCStudio_v3.3\ndk_2_0_0_1"

8. C674x DSP/BIOS PSP Drivers (BIOS PSP Release version 01.30.00.05)
Your version : 1.30.00.05
Required version: 1.30.00.05
Required for : Code generation / device drivers
PSP_EVMC6748_INSTALLDIR="C:\ti\ccsv5\pspdrivers_01_30_00_05"

9. EDMA3 Low Level Driver (EDMA3 LLD 01.10)
Your version : 01.10.00
Required version: 1.10.00 or later
Required for : Device drivers
EDMA3LLD_BIOS5_INSTALLDIR="C:\ti\ccsv5\edma3_01_10_00_01"

10. OMAP-L138/C6747EVM BSL (OMAP-L138 / TMS320C6748 / AM1808 SOM-M1 Gel, CCS Setup, & BSL Files (CCS v4.2.4))
Your version : 2.3.2
Required version: 2.0.0 or later
Required for : Device drivers
BSL_EVMC6748_INSTALLDIR="C:\ti\ccsv5\CCSv4-2-4_with_SOM-M1_BSL_WS"

All configurations are the same,when I compile the model , error is coming as shown below:

### Generating code into build folder: C:\ti\DSP6000_WORK\dream_ticcs
All blocks in block diagram 'dream' are either virtual or have been removed by block reduction optimization or they are inactive variants, therefore there is nothing to simulate. Note, for code generation, block reduction optimization removes all diagram branches terminating in sink blocks that do not participate in code generation. For example, To Workspace and potentially their sources are removed when the MAT-file logging is off
Component: Simulink | Category: Block diagram warning
### Invoking Target Language Compiler on dream.rtw
### Using System Target File: C:\MATLAB\R2016a\toolbox\idelink\foundation\pjtgenerator\rtw\idelink_ert.tlc
### Loading TLC function libraries
### Generating TLC interface API for custom data
### Initial pass through model to cache user defined code
.
### Caching model source code
### Writing header file dream_types.h
### Writing header file dream.h
### Writing header file rtwtypes.h
### Writing source file dream.c
### Writing header file dream_private.h
.
### Writing source file dream_main.c
### Writing header file dream_main.h
### Writing header file MW_c6xxx_csl.h
### Writing source file MW_c6xxx_csl.c
### TLC code generation complete.
### Creating HTML report file dream_codegen_rpt.html
### Creating makefile: C:\ti\DSP6000_WORK\dream_ticcs\dream.mk
### Makefile creation done.
### Building makefile...
The call to idelink_ert_make_rtw_hook, during the exit hook generated the following error:
Error while building the project.

The build process will terminate as a result.
Caused by:
Error while building the project.
The build failed with the following message: "C:/ti/ccsv5/tools/compiler/C6000/bin/cl6x.exe" -I"C:/MATLAB/R2016a/toolbox/idelink/extensions/ticcs/inc" -I"C:/MATLAB/R2016a/simulink/include/sf_runtime" -I"C:/ti/DSP6000_WORK/dream_ticcs" -I"C:/ti/DSP6000_WORK" -I"C:/MATLAB/R2016a/extern/include" -I"C:/MATLAB/R2016a/simulink/include" -I"C:/MATLAB/R2016a/rtw/c/src" -I"C:/MATLAB/R2016a/rtw/c/src/ext_mode/common" -I"C:/MATLAB/R2016a/rtw/c/ert" -D"CHIP_OMAPL138" -D"__TICCSC__" -D"RT" -D"USE_RTMODEL" -mv6740 -D"MODEL=dream" -D"NUMST=1" -D"NCSTATES=0" -D"HAVESTDIO=" -D"ONESTEPFCN=1" -D"TERMFCN=1" -D"MAT_FILE=0" -D"MULTI_INSTANCE_CODE=0" -D"INTEGER_CODE=0" -D"MT=0" -D"CLASSIC_INTERFACE=0" -D"ALLOCATIONFCN=0" -D"TID01EQ=0" -I"C:/ti/ccsv5/tools/compiler/C6000/include" -I"C:/ti/ccsv5/bios_5_41_11_38/packages/ti/bios/include" -I"C:/ti/ccsv5/C6xCSL/include" -fr"./derived/" ./MW_c6xxx_csl.c ./dream.c ./dream_main.c
[MW_c6xxx_csl.c]
".\MW_c6xxx_csl.h", line 19: fatal error: could not open source file "dreamcfg.h"
1 fatal error detected in the compilation of "./MW_c6xxx_csl.c".
Compilation terminated.

>> Compilation failure
gmake: *** [derived/MW_c6xxx_csl.obj] Error 1

Can anyone help me? My email is dreamfly4@1 6 3.com,Thank you so much again.