• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 53 subscribers
  • Views 955 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CCS/TMS320VC5502: UART Baud rate calculation for TMS320VC5502-clk as 30MHZ

Muneeswaran manokaran
Intellectual 650 points
Part Number: TMS320VC5502

Tool/software: Code Composer Studio

Hi ,

     I am Using TMS320VC5502 Proceesor. External Crystal 30MHZ is used. I refer Chip Select Library for C55x  formula as

divisor value = (clk) / (16 x baud rate)

so i calculate divisor value for 1,15,200 Baud rate is 16. But no character display in Hyperterminal.

i measure baudrate using logic analyzer , it was 960000.

How Baudrate calculation works ?? Anybody explain or provide any link?

( Note : From that about measure baudrate , i predict divisor value as 133, get character display in hyper terminal at 115200 baudrate)

Anyother formula ?

 

Thanks

  • 0
    TI__Intellectual 2300 points
    Hello,
    the UART module gets its clock from so called "Slow Peripherals Clock Group". That means Divider D2 is involved which output is SYSCLK2.
    You must check your PLL control registers settings to be able to calculate baud rate properly.
    I suppose you' referring to www.ti.com/.../tms320vc5502.pdf.
    If so you should check "Figure 3-14. Clock Generator Registers"

    Michail
  • 0 in reply to Michail Georgiev
    Intellectual 650 points
    Hi Michail,

    I need to set PLL of 5502 DSP on 200MHZ with a 30MHZ external crystal .In PLLM register which value i can choose to get 200MHz??
    if I am select PLLM=0x0006(6*30=180MHz) or PLLM=0x0007(7*30=210MHz its exceeds 200MHz)

    I substitute following value in PLL setting

    PLLM=0x0006 (180MHz)
    PLLDIV0=0x8000
    PLLDIV1=0x8001
    PLLDIV2=0x8001 (180/2 = 90MHZ)
    PLLDIV3=0x8003


    Now i calculate
    divisor value = (clk) / (16 x baud rate) = 90MHz/(16*115200)=48.8 ~ 49 Divisor value

    But, i didn't get character in Hyperterminal..

    Above Procedur is correct sir?? any solution ?

    Thanks
  • 0 in reply to Muneeswaran manokaran
    TI__Intellectual 2300 points
    Hello,
    you said that external crystal is 30Mhz. So your X2/CLKIN (Master oscillator) is equal to this frequency which is out of specifications.
    For VC5502 this frequency should be between 5 and 20 MHz. You may first correct this and recalculate the desired frequency.
    Since PLL clock is determined by the PLLM register and PLLDIV0 register for example you can choose crystal of 10 or 20MHz and easily achieve 200MHz for the VC5502 clock. After that UART input clock can be adjusted by PLLDIV2 and baud rate controlled by Baud Divisor. Since input crystal is out of specs it is not guaranteed that Clock Generator Module and PLL are functioning properly.

    Michail