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We are in the process of adding information about LUT and HIST as part of 00.06 training material. But this will most likely be available by May 2020.
The lookup hardware is implemented in L1D memory which is a 16x64b bank memory were the CPU can send 16 independent addresses to each bank. This in-effect emulates the lookup/histrogram type of access.
On reset, the C71x DSP partitions the L1D as 32KB of cache and 16KB of SRAM. You have an option of reducing the cache size which increases the SRAM size.
For example if L1D cache is reduced to 16KB then L1D SRAM becomes 32KB.
You also have an option of choosing the number of ways, table size, element to be indexed and other properties of the LUT.
To get a full list of options you can take a look at this file,
I also recommend you to take a look at this kernel, \c7x_dsp_code_samples_adv\c7x_hough_lines\alg\VXLIB_houghLineFromList_i16u_o16u.c for an example usage of LUT and HIST
