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Original question:
Tool/software: Code Composer Studio
Dear Sir,
We have used
TIDL patch : tidl_j7_01_01_01_01
MMA Library : mmalib_01_01_00_02
We tried to import the Caffe based model with the below configuration
numparambits=numfeaturebits= 16
quantizationStyle= 3
On the PC emulation mode, results are correctly dumped i.e., images(output) but when tried to run the same model as Standalone on target the output images are not properly dumped.
Please find the attached zip file for your reference.output.zip
Attached file has the PC Emulation and Target dumped results for the same input and same model.
What could be the possible reason for this?
Kindly help us to resolve the same.
Thanks and Regards,
Vyom Mishra
Could you enable layer level traces and compare the same between PC emulation and Target. Share the details about the first mismatching layer.
Dear Sir,
I have followed the guide
"set enableLayerPerfTraces = 1 in inference configuration file to enable layer level performance."
Please find the inference config file for your reference
inFileFormat = 2 postProcType = 2 netBinFile = "/home/sithara/ti/j8/psdk_rtos_auto_j7_06_02_00_21/tidl_j7_01_01_01_01/ti_dl/test/testvecs/config/tidl_models/caffe/mobilenet_flip_false_old/tidl_net_flip_false_l1.bin" ioConfigFile = "/home/sithara/ti/j8/psdk_rtos_auto_j7_06_02_00_21/tidl_j7_01_01_01_01/ti_dl/test/testvecs/config/tidl_models/caffe/mobilenet_flip_false_old/tidl_io_flip_false_l11.bin" outData = "testvecs/output/msi_mobilenet_flip_false.bin" inData = "/home/sithara/tidl_j7_01_01_00_10/ti_dl/test/testvecs/config/det.txt" debugTraceLevel = 1 writeTraceLevel = 0 numFrames = 10 enableLayerPerfTraces = 1
In PC Emulation side, We observed the Null values in the Performance traces please find it for your reference
sithara@ubuntu:~/ti/j8/psdk_rtos_auto_j7_06_02_00_21/tidl_j7_01_01_01_01/ti_dl/test$ ./PC_dsp_test_dl_algo.out Processing config file #0 : testvecs/config/infer/public/caffe/tidl_infer_mobilenet_flip_false.txt Instance created for testvecs/config/infer/public/caffe/tidl_infer_mobilenet_flip_false.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. Network Cycles 0 Layer, Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger, paddingWait,LayerWithoutPad,LayerHandleCopy, BackupCycles, RestoreCycles, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 11, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 13, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 17, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 18, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 19, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 20, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 21, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 22, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 23, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 24, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 25, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 26, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 27, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 28, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 29, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 34, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 35, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 36, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 37, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 38, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 39, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 40, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 41, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 42, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 43, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 44, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 45, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 46, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 47, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 48, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 49, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 50, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 51, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 52, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 53, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 54, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 55, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 56, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 57, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 58, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 59, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 61, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 62, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 63, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, T 3009.04 ... .... .....
In target Side:
While using the same inference config file we got non-zero values, please find it for your reference
Sciclient Dev Group 00 initilization done
Sciclient Dev Group 01 initilization started
DMSC Board Configuration with Debug enable
DMSC Firmware Version 19.12.1-v 19.12a (Terrific Lla
Firmware revision 0x13
ABI revision 2.9
[C71X_0] SCICLIENT: DMSC FW version [19.12.1-v 19.12a (Terrific Lla]
SCICLIENT: DMSC FW revision 0x13
SCICLIENT: DMSC FW ABI revision 2.9
Processing config file #0 : testvecs/config/infer/public/caffe/tidl_infer_mobilenet_flip_false.txt
Syncd
Instance created for testvecs/config/infer/public/caffe/tidl_infer_mobilenet_flip_false.txt
----------------------- TIDL Process with TARGET DATA FLOW ------------------------
# 0 . ..
Network Cycles 33125822
Layer, Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger, paddingWait,LayerWithoutPad,LayerHandleCopy, BackupCycles, RestoreCycles,
1, 24016982, 23985029, 23985301, 228, 64, 16, 0, 0, 36, 23985029, 19393, 63, 23992844, 0, 0, 0,
2, 159336, 120353, 121661, 8170, 3649, 18, 874, 14, 505, 4125, 16580, 185, 139904, 5400, 0, 0,
3, 138620, 119253, 124428, 4339, 2799, 10, 0, 0, 584, 6686, 690, 186, 135335, 1854, 0, 0,
4, 115890, 98782, 100639, 5701, 3412, 18, 17, 17, 239, 4741, 1079, 36, 112769, 3749, 0, 0,
5, 133396, 112902, 122103, 3913, 2852, 10, 0, 0, 183, 3385, 126, 100, 131468, 1336, 0, 0,
6, 140506, 123298, 124126, 5676, 4332, 18, 10, 7, 508, 4084, 1591, 36, 137201, 3643, 0, 0,
7, 122431, 108941, 111776, 2691, 2786, 3, 0, 0, 265, 6663, 112, 100, 120226, 1296, 0, 0,
8, 140754, 125150, 126846, 5387, 4482, 18, 10, 7, 211, 4143, 112, 29, 139057, 3502, 0, 0,
9, 67437, 53961, 56736, 3321, 2786, 3, 0, 0, 356, 3320, 142, 29, 65283, 1469, 0, 0,
10, 77770, 60997, 61492, 5260, 5457, 11, 10, 7, 89, 14062, 1412, 29, 74329, 3345, 0, 0,
11, 66908, 55343, 56698, 3191, 3225, 3, 0, 0, 93, 6825, 111, 117, 65202, 1510, 0, 0,
12, 110672, 92970, 93820, 5325, 6806, 18, 10, 7, 231, 7284, 112, 29, 108986, 3186, 0, 0,
13, 41438, 29577, 30875, 3648, 3192, 3, 0, 0, 222, 3568, 150, 29, 39605, 1688, 0, 0,
14, 65810, 45688, 45942, 5030, 9315, 11, 10, 7, 89, 15195, 1152, 29, 62399, 3387, 0, 0,
15, 43020, 30185, 30858, 2649, 4428, 3, 0, 0, 82, 7351, 126, 1140, 39933, 1313, 0, 0,
16, 106200, 82921, 83688, 4936, 13470, 11, 10, 7, 87, 2914, 112, 29, 104716, 3374, 0, 0,
17, 41635, 29788, 30605, 3078, 4005, 3, 0, 0, 287, 7349, 140, 29, 39945, 1203, 0, 0,
18, 105500, 82726, 83382, 4718, 13601, 11, 10, 7, 190, 2914, 112, 29, 104003, 3201, 0, 0,
19, 41622, 29806, 30486, 2683, 4067, 3, 0, 0, 533, 7349, 126, 29, 40027, 1152, 0, 0,
20, 105946, 82850, 83515, 4944, 13669, 11, 10, 7, 87, 2914, 112, 29, 104402, 3107, 0, 0,
21, 41391, 30050, 30715, 2632, 4157, 3, 0, 0, 82, 7351, 112, 29, 39379, 1345, 0, 0,
22, 105554, 82523, 83179, 4875, 13656, 11, 11, 7, 190, 2914, 112, 29, 103858, 3129, 0, 0,
23, 41368, 29940, 30605, 2422, 4135, 3, 0, 0, 225, 7351, 112, 29, 39322, 1058, 0, 0,
24, 105857, 82640, 83328, 4783, 13811, 11, 10, 7, 87, 2914, 112, 29, 104101, 3257, 0, 0,
25, 42638, 31250, 32076, 2653, 4115, 3, 0, 0, 82, 7494, 137, 29, 40834, 1332, 0, 0,
26, 80656, 45803, 46193, 5125, 24026, 11, 10, 7, 89, 5383, 1472, 29, 77373, 3356, 0, 0,
27, 50837, 33450, 33961, 3156, 6668, 3, 0, 0, 186, 16546, 109, 3177, 46026, 1394, 0, 0,
28, 170240, 106566, 114911, 4822, 3067, 18, 10, 42443, 102, 1119, 881, 102, 167532, 2894, 0, 0,
29, 43799, 5462, 9196, 1988, 4103, 16, 0, 0, 252, 2539, 6407, 3735, 32027, 0, 0, 0,
30, 22453, 2266, 4528, 1446, 2401, 9, 0, 0, 66, 1130, 3770, 123, 16657, 0, 0, 0,
31, 18813, 1252, 3159, 793, 2055, 9, 0, 0, 138, 613, 3013, 296, 13366, 0, 0, 0,
32, 25631, 12486, 12994, 2976, 4016, 3, 0, 0, 185, 5750, 112, 1004, 22927, 1652, 0, 0,
33, 76345, 16564, 18959, 5282, 4059, 11, 10, 42384, 201, 996, 1248, 36, 73465, 2593, 0, 0,
34, 31783, 5616, 5711, 3398, 14825, 11, 10, 14, 192, 5616, 170, 3288, 26641, 2335, 0, 0,
35, 9787, 0, 0, 0, 0, 0, 0, 0, 0, 0, 249, 36, 7578, 0, 0, 0,
36, 24634, 5230, 5384, 5235, 9401, 11, 10, 7, 307, 5230, 112, 29, 22975, 3042, 0, 0,
37, 6969, 0, 0, 0, 0, 0, 0, 0, 0, 0, 112, 29, 4937, 0, 0, 0,
38, 28595, 15584, 16065, 3238, 4788, 3, 0, 0, 162, 7315, 112, 29, 26472, 1875, 0, 0,
39, 74979, 16071, 18601, 4374, 4110, 11, 10, 42473, 203, 982, 1289, 29, 71946, 2345, 0, 0,
40, 32276, 5225, 5405, 4144, 15187, 11, 10, 7, 87, 5225, 112, 3184, 27024, 2361, 0, 0,
41, 12642, 0, 0, 0, 0, 0, 0, 0, 0, 0, 274, 29, 10946, 0, 0, 0,
42, 24500, 5431, 5668, 4722, 9752, 11, 10, 7, 87, 5431, 181, 29, 22566, 2519, 0, 0,
43, 8108, 0, 0, 0, 0, 0, 0, 0, 0, 0, 253, 29, 6466, 0, 0, 0,
44, 34284, 21223, 21593, 3068, 5140, 3, 0, 0, 95, 10396, 125, 29, 32465, 1362, 0, 0,
45, 103017, 43253, 48291, 4847, 2109, 11, 10, 42782, 100, 1056, 1367, 29, 100189, 2580, 0, 0,
46, 48215, 15150, 15331, 4866, 18294, 11, 2220, 7, 203, 15150, 112, 2651, 43162, 2975, 0, 0,
47, 30170, 0, 0, 0, 0, 0, 0, 0, 0, 0, 119, 29, 28473, 0, 0, 0,
48, 35961, 14555, 14708, 4520, 10174, 71, 2190, 7, 89, 14555, 171, 29, 34261, 2627, 0, 0,
49, 17991, 0, 0, 0, 0, 0, 0, 0, 0, 0, 112, 29, 16302, 0, 0, 0,
50, 48492, 33827, 34327, 3193, 6655, 3, 0, 0, 344, 16545, 170, 29, 46845, 1466, 0, 0,
51, 170889, 106384, 114794, 4835, 3057, 11, 17, 42204, 87, 1029, 1506, 29, 167568, 2865, 0, 0,
52, 78808, 45192, 45756, 4871, 18469, 11, 2171, 7, 87, 15107, 112, 3127, 73909, 3173, 0, 0,
53, 81416, 0, 0, 0, 0, 0, 0, 0, 0, 0, 164, 29, 79458, 0, 0, 0,
54, 66537, 44154, 44674, 5008, 10252, 11, 2164, 7, 137, 14700, 140, 29, 64444, 3135, 0, 0,
55, 45906, 0, 0, 0, 0, 0, 0, 0, 0, 0, 119, 29, 43881, 0, 0, 0,
56, 43594, 30399, 31188, 3738, 4143, 3, 0, 0, 237, 7351, 126, 29, 41580, 1557, 0, 0,
57, 201799, 165541, 166754, 5469, 23304, 11, 17, 21, 87, 5311, 1426, 29, 198444, 3632, 0, 0,
58, 194649, 160979, 163110, 5471, 13646, 11, 4212, 7, 118, 14692, 139, 3900, 188779, 3539, 0, 0,
59, 184517, 0, 0, 0, 0, 0, 0, 0, 0, 0, 272, 29, 182313, 0, 0, 0,
60, 25400, 2227, 2555, 4155, 2910, 52, 0, 0, 509, 2227, 249, 142, 21360, 0, 0, 0,
61, 187781, 161661, 163792, 5878, 8660, 11, 4204, 7, 144, 15181, 112, 29, 185436, 3614, 0, 0,
62, 109019, 0, 0, 0, 0, 0, 0, 0, 0, 0, 450, 29, 106849, 0, 0, 0,
63, 20130, 1433, 1708, 4463, 1913, 45, 0, 0, 402, 1433, 116, 29, 16757, 0, 0, 0,
64, 4356042, 0, 0, 0, 0, 0, 0, 0, 0, 0, 733, 65, 4351920, 0, 0, 0,
TSC Mega Cycles = 6343.74 ... .... .....Kindly help us to resolve the PC Emulation issue.
Thanks and Regards,
Vyom Mishra
Vyom Mishra,
The performance numbers on PC emulation mode are supposed to be zero, as PC emulation is not supposed to be a performance oriented
- Subhajit
Dear Sir,
Thanks for the information!
We will share all the details of the First layer mismatch soon.
Thanks and Regards,
Vyom Mishra
Dear Sir,
I am sharing you the channels wise images for Layer-0, Layer-1 and Layer-2 dumps for you referencelayer-wise-channels_output.zip
Please find the Netlog for your reference
Num of Layer Detected : 64
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Num|TIDL Layer Name |Out Data Name |Group |#Ins |#Outs |Inbuf Ids |Outbuf Id |In NCHW |Out NCHW |MACS |
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0|TIDL_DataLayer |data | 0| -1| 1| x x x x x x x x | 0 | 0 0 0 0 | 1 3 512 512 | 0 |
1|TIDL_BatchNormLayer |data/bias | 0| 1| 1| 0 x x x x x x x | 1 | 1 3 512 512 | 1 3 512 512 | 786432 |
2|TIDL_ConvolutionLayer |conv1 | 0| 1| 1| 1 x x x x x x x | 2 | 1 3 512 512 | 1 16 256 256 | 30408704 |
3|TIDL_ConvolutionLayer |conv2_1/dw | 0| 1| 1| 2 x x x x x x x | 3 | 1 16 256 256 | 1 16 256 256 | 11534336 |
4|TIDL_ConvolutionLayer |conv2_1/sep | 0| 1| 1| 3 x x x x x x x | 4 | 1 16 256 256 | 1 32 256 256 | 37748736 |
5|TIDL_ConvolutionLayer |conv2_2/dw | 0| 1| 1| 4 x x x x x x x | 5 | 1 32 256 256 | 1 32 128 128 | 5767168 |
6|TIDL_ConvolutionLayer |conv2_2/sep | 0| 1| 1| 5 x x x x x x x | 6 | 1 32 128 128 | 1 64 128 128 | 35651584 |
7|TIDL_ConvolutionLayer |conv3_1/dw | 0| 1| 1| 6 x x x x x x x | 7 | 1 64 128 128 | 1 64 128 128 | 11534336 |
8|TIDL_ConvolutionLayer |conv3_1/sep | 0| 1| 1| 7 x x x x x x x | 8 | 1 64 128 128 | 1 64 128 128 | 69206016 |
9|TIDL_ConvolutionLayer |conv3_2/dw | 0| 1| 1| 8 x x x x x x x | 9 | 1 64 128 128 | 1 64 64 64 | 2883584 |
10|TIDL_ConvolutionLayer |conv3_2/sep | 0| 1| 1| 9 x x x x x x x | 10 | 1 64 64 64 | 1 128 64 64 | 34603008 |
11|TIDL_ConvolutionLayer |conv4_1/dw | 0| 1| 1| 10 x x x x x x x | 11 | 1 128 64 64 | 1 128 64 64 | 5767168 |
12|TIDL_ConvolutionLayer |conv4_1/sep | 0| 1| 1| 11 x x x x x x x | 12 | 1 128 64 64 | 1 128 64 64 | 68157440 |
13|TIDL_ConvolutionLayer |conv4_2/dw | 0| 1| 1| 12 x x x x x x x | 13 | 1 128 64 64 | 1 128 32 32 | 1441792 |
14|TIDL_ConvolutionLayer |conv4_2/sep | 0| 1| 1| 13 x x x x x x x | 14 | 1 128 32 32 | 1 256 32 32 | 34078720 |
15|TIDL_ConvolutionLayer |conv5_1/dw | 0| 1| 1| 14 x x x x x x x | 15 | 1 256 32 32 | 1 256 32 32 | 2883584 |
16|TIDL_ConvolutionLayer |conv5_1/sep | 0| 1| 1| 15 x x x x x x x | 16 | 1 256 32 32 | 1 256 32 32 | 67633152 |
17|TIDL_ConvolutionLayer |conv5_2/dw | 0| 1| 1| 16 x x x x x x x | 17 | 1 256 32 32 | 1 256 32 32 | 2883584 |
18|TIDL_ConvolutionLayer |conv5_2/sep | 0| 1| 1| 17 x x x x x x x | 18 | 1 256 32 32 | 1 256 32 32 | 67633152 |
19|TIDL_ConvolutionLayer |conv5_3/dw | 0| 1| 1| 18 x x x x x x x | 19 | 1 256 32 32 | 1 256 32 32 | 2883584 |
20|TIDL_ConvolutionLayer |conv5_3/sep | 0| 1| 1| 19 x x x x x x x | 20 | 1 256 32 32 | 1 256 32 32 | 67633152 |
21|TIDL_ConvolutionLayer |conv5_4/dw | 0| 1| 1| 20 x x x x x x x | 21 | 1 256 32 32 | 1 256 32 32 | 2883584 |
22|TIDL_ConvolutionLayer |conv5_4/sep | 0| 1| 1| 21 x x x x x x x | 22 | 1 256 32 32 | 1 256 32 32 | 67633152 |
23|TIDL_ConvolutionLayer |conv5_5/dw | 0| 1| 1| 22 x x x x x x x | 23 | 1 256 32 32 | 1 256 32 32 | 2883584 |
24|TIDL_ConvolutionLayer |ctx_output1/dw | 0| 1| 1| 22 x x x x x x x | 24 | 1 256 32 32 | 1 256 32 32 | 2883584 |
25|TIDL_ConvolutionLayer |conv5_5/sep | 0| 1| 1| 23 x x x x x x x | 25 | 1 256 32 32 | 1 256 32 32 | 67633152 |
26|TIDL_ConvolutionLayer |ctx_output1/sep | 0| 1| 1| 24 x x x x x x x | 26 | 1 256 32 32 | 1 512 32 32 | 135266304 |
27|TIDL_ConvolutionLayer |conv5_6/dw | 0| 1| 1| 25 x x x x x x x | 27 | 1 256 32 32 | 1 256 16 16 | 720896 |
28|TIDL_ConvolutionLayer |ctx_output1/sep/relu_mbox_loc_perm | 0| 1| 1| 26 x x x x x x x | 28 | 1 512 32 32 | 1 16 32 32 | 75497472 |
29|TIDL_ConvolutionLayer |ctx_output2/dw | 0| 1| 1| 25 x x x x x x x | 29 | 1 256 32 32 | 1 256 32 32 | 2883584 |
30|TIDL_ConvolutionLayer |ctx_output1/sep/relu_mbox_conf_perm | 0| 1| 1| 26 x x x x x x x | 30 | 1 512 32 32 | 1 8 32 32 | 37748736 |
31|TIDL_FlattenLayer |ctx_output1/sep/relu_mbox_loc_flat | 0| 1| 1| 28 x x x x x x x | 31 | 1 16 32 32 | 1 1 1 16384 | 16384 |
32|TIDL_FlattenLayer |ctx_output1/sep/relu_mbox_conf_flat | 0| 1| 1| 30 x x x x x x x | 32 | 1 8 32 32 | 1 1 1 8192 | 8192 |
33|TIDL_ConvolutionLayer |conv5_6/sep | 0| 1| 1| 27 x x x x x x x | 33 | 1 256 16 16 | 1 512 16 16 | 33816576 |
34|TIDL_ConvolutionLayer |ctx_output2/sep | 0| 1| 1| 29 x x x x x x x | 34 | 1 256 32 32 | 1 512 32 32 | 135266304 |
35|TIDL_ConvolutionLayer |conv6/dw | 0| 1| 1| 33 x x x x x x x | 35 | 1 512 16 16 | 1 512 16 16 | 1441792 |
36|TIDL_ConvolutionLayer |ctx_output2/sep/relu_mbox_loc_perm | 0| 1| 1| 34 x x x x x x x | 36 | 1 512 32 32 | 1 16 32 32 | 75497472 |
37|TIDL_ConvolutionLayer |ctx_output3/dw | 0| 1| 1| 33 x x x x x x x | 37 | 1 512 16 16 | 1 256 16 16 | 1310720 |
38|TIDL_ConvolutionLayer |ctx_output2/sep/relu_mbox_conf_perm | 0| 1| 1| 34 x x x x x x x | 38 | 1 512 32 32 | 1 8 32 32 | 37748736 |
39|TIDL_FlattenLayer |ctx_output2/sep/relu_mbox_loc_flat | 0| 1| 1| 36 x x x x x x x | 39 | 1 16 32 32 | 1 1 1 16384 | 16384 |
40|TIDL_FlattenLayer |ctx_output2/sep/relu_mbox_conf_flat | 0| 1| 1| 38 x x x x x x x | 40 | 1 8 32 32 | 1 1 1 8192 | 8192 |
41|TIDL_ConvolutionLayer |conv6/sep | 0| 1| 1| 35 x x x x x x x | 41 | 1 512 16 16 | 1 512 16 16 | 67371008 |
42|TIDL_ConvolutionLayer |ctx_output3/sep | 0| 1| 1| 37 x x x x x x x | 42 | 1 256 16 16 | 1 512 16 16 | 33816576 |
43|TIDL_PoolingLayer |pool6 | 0| 1| 1| 41 x x x x x x x | 43 | 1 512 16 16 | 1 512 8 8 | 131072 |
44|TIDL_ConvolutionLayer |ctx_output3/sep/relu_mbox_loc_perm | 0| 1| 1| 42 x x x x x x x | 44 | 1 512 16 16 | 1 16 16 16 | 18874368 |
45|TIDL_ConvolutionLayer |ctx_output4/dw | 0| 1| 1| 41 x x x x x x x | 45 | 1 512 16 16 | 1 256 16 16 | 1310720 |
46|TIDL_ConvolutionLayer |ctx_output5/dw | 0| 1| 1| 43 x x x x x x x | 46 | 1 512 8 8 | 1 256 8 8 | 327680 |
47|TIDL_ConvolutionLayer |ctx_output3/sep/relu_mbox_conf_perm | 0| 1| 1| 42 x x x x x x x | 47 | 1 512 16 16 | 1 8 16 16 | 9437184 |
48|TIDL_FlattenLayer |ctx_output3/sep/relu_mbox_loc_flat | 0| 1| 1| 44 x x x x x x x | 48 | 1 16 16 16 | 1 1 1 4096 | 4096 |
49|TIDL_FlattenLayer |ctx_output3/sep/relu_mbox_conf_flat | 0| 1| 1| 47 x x x x x x x | 49 | 1 8 16 16 | 1 1 1 2048 | 2048 |
50|TIDL_ConvolutionLayer |ctx_output4/sep | 0| 1| 1| 45 x x x x x x x | 50 | 1 256 16 16 | 1 512 16 16 | 33816576 |
51|TIDL_ConvolutionLayer |ctx_output5/sep | 0| 1| 1| 46 x x x x x x x | 51 | 1 256 8 8 | 1 512 8 8 | 8454144 |
52|TIDL_ConvolutionLayer |ctx_output4/sep/relu_mbox_loc_perm | 0| 1| 1| 50 x x x x x x x | 52 | 1 512 16 16 | 1 24 16 16 | 28311552 |
53|TIDL_ConvolutionLayer |ctx_output5/sep/relu_mbox_loc_perm | 0| 1| 1| 51 x x x x x x x | 53 | 1 512 8 8 | 1 32 8 8 | 9437184 |
54|TIDL_ConvolutionLayer |ctx_output4/sep/relu_mbox_conf_perm | 0| 1| 1| 50 x x x x x x x | 54 | 1 512 16 16 | 1 12 16 16 | 14155776 |
55|TIDL_ConvolutionLayer |ctx_output5/sep/relu_mbox_conf_perm | 0| 1| 1| 51 x x x x x x x | 55 | 1 512 8 8 | 1 16 8 8 | 4718592 |
56|TIDL_FlattenLayer |ctx_output4/sep/relu_mbox_loc_flat | 0| 1| 1| 52 x x x x x x x | 56 | 1 24 16 16 | 1 1 1 6144 | 6144 |
57|TIDL_FlattenLayer |ctx_output5/sep/relu_mbox_loc_flat | 0| 1| 1| 53 x x x x x x x | 57 | 1 32 8 8 | 1 1 1 2048 | 2048 |
58|TIDL_FlattenLayer |ctx_output4/sep/relu_mbox_conf_flat | 0| 1| 1| 54 x x x x x x x | 58 | 1 12 16 16 | 1 1 1 3072 | 3072 |
59|TIDL_FlattenLayer |ctx_output5/sep/relu_mbox_conf_flat | 0| 1| 1| 55 x x x x x x x | 59 | 1 16 8 8 | 1 1 1 1024 | 1024 |
60|TIDL_ConcatLayer |mbox_loc | 0| 5| 1| 31 39 48 56 57 x x x | 60 | 1 1 1 16384 | 1 1 1 45056 | 45056 |
61|TIDL_ConcatLayer |mbox_conf_flatten | 0| 5| 1| 32 40 49 58 59 x x x | 61 | 1 1 1 8192 | 1 1 1 22528 | 22528 |
62|TIDL_DetectionOutputLayer |detection_out | 0| 2| 1| 60 61 x x x x x x | 62 | 1 1 1 45056 | 1 1 1 1404 | 0 |
63|TIDL_DataLayer |detection_out | 0| 1| -1| 62 x x x x x x x | 0 | 1 1 1 1404 | 0 0 0 0 | 0 |
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Total Giga Macs : 1.4725
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Observations:
a) Layer-0: It has no such pixels glitches
b) Layer-1 and Layer 2: It has a series of pixels glitches which is also found in the output image dumps of the model at Target side only.
Note: These glitches of pixels in the output are not observed on PC Emulation and Import side, it is present only at Target side.
Kindly help us to resolve the same.
Thanks and Regards,
Vyom Mishra
We want to update this thread with some information. Subhajit will post further.
Vyom Mishra,
I remember responding to this thread on 14th Jun, but I cannot see my response right now.
We have recently released a new SDK. Can you try to reproduce the issue on that?
- Subhajit
