CCS: TDA4x: Issue in image dumps on target(Standalone) for caffe based model

Vyom Mishra1

Genius 4590 points

Tool/software: Code Composer Studio

Dear Sir,

We have used

TIDL patch : tidl_j7_01_01_01_01

MMA Library : mmalib_01_01_00_02

We tried to import the Caffe based model with the below configuration

numparambits=numfeaturebits= 16

quantizationStyle= 3

On the PC emulation mode, results are correctly dumped i.e., images(output) but when tried to run the same model as Standalone on target the output images are not properly dumped.

Please find the attached zip file for your reference.output.zip

Attached file has the PC Emulation and Target dumped results for the same input and same model.

What could be the possible reason for this?

Kindly help us to resolve the same.

Thanks and Regards,

Vyom Mishra

over 5 years ago

0 kumar.desappan over 5 years ago

TI__Mastermind 22145 points

Could you enable layer level traces and compare the same between PC emulation and Target. Share the details about the first mismatching layer.

0 Vyom Mishra1 over 5 years ago in reply to kumar.desappan

Genius 4590 points

Dear Sir,

I have followed the guide

"set enableLayerPerfTraces = 1 in inference configuration file to enable layer level performance."

Please find the inference config file for your reference

Fullscreen tidl_infer_mobilenet_flip_false.txt Download

inFileFormat    = 2
postProcType = 2
netBinFile      = "/home/sithara/ti/j8/psdk_rtos_auto_j7_06_02_00_21/tidl_j7_01_01_01_01/ti_dl/test/testvecs/config/tidl_models/caffe/mobilenet_flip_false_old/tidl_net_flip_false_l1.bin"
ioConfigFile    = "/home/sithara/ti/j8/psdk_rtos_auto_j7_06_02_00_21/tidl_j7_01_01_01_01/ti_dl/test/testvecs/config/tidl_models/caffe/mobilenet_flip_false_old/tidl_io_flip_false_l11.bin"
outData =   "testvecs/output/msi_mobilenet_flip_false.bin"
inData  =   "/home/sithara/tidl_j7_01_01_00_10/ti_dl/test/testvecs/config/det.txt"
debugTraceLevel = 1
writeTraceLevel = 0
numFrames = 10
enableLayerPerfTraces = 1

In PC Emulation side, We observed the Null values in the Performance traces please find it for your reference

Fullscreen PC_Emul.txt Download

sithara@ubuntu:~/ti/j8/psdk_rtos_auto_j7_06_02_00_21/tidl_j7_01_01_01_01/ti_dl/test$ ./PC_dsp_test_dl_algo.out

Processing config file #0 : testvecs/config/infer/public/caffe/tidl_infer_mobilenet_flip_false.txt

Instance created for testvecs/config/infer/public/caffe/tidl_infer_mobilenet_flip_false.txt
----------------------- TIDL Process with REF_ONLY FLOW ------------------------

# 0 . ..
Network Cycles 0
Layer, Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger, paddingWait,LayerWithoutPad,LayerHandleCopy, BackupCycles, RestoreCycles,
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T 3009.04 ... .... .....

In target Side:

While using the t-1a84591e31034fac832d29ed8584666c1239583462_code-editor-fs">Fullscreen //e2e.ti.com/cfs-filesystemfile/__key/communityserver-discussions-components-files/81/target.txt?_=637230678280000000" target.txt">target.txt //e2e.ti.com/cfs-filesystemfile/__key/communityserver-discussions-components-files/81/target.txt?_=637230678280000000" target.txt">Download 84591e31034fac832d29ed8584666c1239583462_code-editor" 22px;min-width:1230px;margin:0px;" Dev Group 00 initilization done Group 01 initilization started with Debug enable Version 19.12.1-v19.12a (Terrific Lla DMSC FW version [19.12.1-v19.12a (Terrific Lla] file #0 : testvecs/config/infer/public/caffe/tidl_infer_mobilenet_flip_false.txt testvecs/config/infer/public/caffe/tidl_infer_mobilenet_flip_false.txt TIDL Process with TARGET DATA FLOW ------------------------ Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, 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evolutionCodeEditor('fullscreen', false); evolutionCodeEditor('fullscreen', true);

Kindly help us to resolve the PC Emulation issue.

Thanks and Regards,

Vyom Mishra

0 Subhajit Paul over 5 years ago in reply to Vyom Mishra1

TI__Expert 7015 points

Vyom Mishra,

The performance numbers on PC emulation mode are supposed to be zero, as PC emulation is not supposed to be a performance oriented

- Subhajit

0 Vyom Mishra1 over 5 years ago in reply to Subhajit Paul

Genius 4590 points

Dear Sir,

Thanks for the information!

We will share all the details of the First layer mismatch soon.

Thanks and Regards,

Vyom Mishra

0 Vyom Mishra1 over 5 years ago in reply to kumar.desappan

Genius 4590 points

Dear Sir,

I am sharing you the channels wise images for Layer-0, Layer-1 and Layer-2 dumps for you referencelayer-wise-channels_output.zip

Please find the Netlog for your reference

Fullscreen tidl_net_flip_false_l1.bin_netLog.txt Download

Num of Layer Detected :  64 
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  Num|TIDL Layer Name               |Out Data Name                                     |Group |#Ins  |#Outs |Inbuf Ids                       |Outbuf Id |In NCHW                             |Out NCHW                            |MACS       |
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    0|TIDL_DataLayer                |data                                              |     0|    -1|     1|  x   x   x   x   x   x   x   x |  0       |       0        0        0        0 |       1        3      512      512 |         0 |
    1|TIDL_BatchNormLayer           |data/bias                                         |     0|     1|     1|  0   x   x   x   x   x   x   x |  1       |       1        3      512      512 |       1        3      512      512 |    786432 |
    2|TIDL_ConvolutionLayer         |conv1                                             |     0|     1|     1|  1   x   x   x   x   x   x   x |  2       |       1        3      512      512 |       1       16      256      256 |  30408704 |
    3|TIDL_ConvolutionLayer         |conv2_1/dw                                        |     0|     1|     1|  2   x   x   x   x   x   x   x |  3       |       1       16      256      256 |       1       16      256      256 |  11534336 |
    4|TIDL_ConvolutionLayer         |conv2_1/sep                                       |     0|     1|     1|  3   x   x   x   x   x   x   x |  4       |       1       16      256      256 |       1       32      256      256 |  37748736 |
    5|TIDL_ConvolutionLayer         |conv2_2/dw                                        |     0|     1|     1|  4   x   x   x   x   x   x   x |  5       |       1       32      256      256 |       1       32      128      128 |   5767168 |
    6|TIDL_ConvolutionLayer         |conv2_2/sep                                       |     0|     1|     1|  5   x   x   x   x   x   x   x |  6       |       1       32      128      128 |       1       64      128      128 |  35651584 |
    7|TIDL_ConvolutionLayer         |conv3_1/dw                                        |     0|     1|     1|  6   x   x   x   x   x   x   x |  7       |       1       64      128      128 |       1       64      128      128 |  11534336 |
    8|TIDL_ConvolutionLayer         |conv3_1/sep                                       |     0|     1|     1|  7   x   x   x   x   x   x   x |  8       |       1       64      128      128 |       1       64      128      128 |  69206016 |
    9|TIDL_ConvolutionLayer         |conv3_2/dw                                        |     0|     1|     1|  8   x   x   x   x   x   x   x |  9       |       1       64      128      128 |       1       64       64       64 |   2883584 |
   10|TIDL_ConvolutionLayer         |conv3_2/sep                                       |     0|     1|     1|  9   x   x   x   x   x   x   x | 10       |       1       64       64       64 |       1      128       64       64 |  34603008 |
   11|TIDL_ConvolutionLayer         |conv4_1/dw                                        |     0|     1|     1| 10   x   x   x   x   x   x   x | 11       |       1      128       64       64 |       1      128       64       64 |   5767168 |
   12|TIDL_ConvolutionLayer         |conv4_1/sep                                       |     0|     1|     1| 11   x   x   x   x   x   x   x | 12       |       1      128       64       64 |       1      128       64       64 |  68157440 |
   13|TIDL_ConvolutionLayer         |conv4_2/dw                                        |     0|     1|     1| 12   x   x   x   x   x   x   x | 13       |       1      128       64       64 |       1      128       32       32 |   1441792 |
   14|TIDL_ConvolutionLayer         |conv4_2/sep                                       |     0|     1|     1| 13   x   x   x   x   x   x   x | 14       |       1      128       32       32 |       1      256       32       32 |  34078720 |
   15|TIDL_ConvolutionLayer         |conv5_1/dw                                        |     0|     1|     1| 14   x   x   x   x   x   x   x | 15       |       1      256       32       32 |       1      256       32       32 |   2883584 |
   16|TIDL_ConvolutionLayer         |conv5_1/sep                                       |     0|     1|     1| 15   x   x   x   x   x   x   x | 16       |       1      256       32       32 |       1      256       32       32 |  67633152 |
   17|TIDL_ConvolutionLayer         |conv5_2/dw                                        |     0|     1|     1| 16   x   x   x   x   x   x   x | 17       |       1      256       32       32 |       1      256       32       32 |   2883584 |
   18|TIDL_ConvolutionLayer         |conv5_2/sep                                       |     0|     1|     1| 17   x   x   x   x   x   x   x | 18       |       1      256       32       32 |       1      256       32       32 |  67633152 |
   19|TIDL_ConvolutionLayer         |conv5_3/dw                                        |     0|     1|     1| 18   x   x   x   x   x   x   x | 19       |       1      256       32       32 |       1      256       32       32 |   2883584 |
   20|TIDL_ConvolutionLayer         |conv5_3/sep                                       |     0|     1|     1| 19   x   x   x   x   x   x   x | 20       |       1      256       32       32 |       1      256       32       32 |  67633152 |
   21|TIDL_ConvolutionLayer         |conv5_4/dw                                        |     0|     1|     1| 20   x   x   x   x   x   x   x | 21       |       1      256       32       32 |       1      256       32       32 |   2883584 |
   22|TIDL_ConvolutionLayer         |conv5_4/sep                                       |     0|     1|     1| 21   x   x   x   x   x   x   x | 22       |       1      256       32       32 |       1      256       32       32 |  67633152 |
   23|TIDL_ConvolutionLayer         |conv5_5/dw                                        |     0|     1|     1| 22   x   x   x   x   x   x   x | 23       |       1      256       32       32 |       1      256       32       32 |   2883584 |
   24|TIDL_ConvolutionLayer         |ctx_output1/dw                                    |     0|     1|     1| 22   x   x   x   x   x   x   x | 24       |       1      256       32       32 |       1      256       32       32 |   2883584 |
   25|TIDL_ConvolutionLayer         |conv5_5/sep                                       |     0|     1|     1| 23   x   x   x   x   x   x   x | 25       |       1      256       32       32 |       1      256       32       32 |  67633152 |
   26|TIDL_ConvolutionLayer         |ctx_output1/sep                                   |     0|     1|     1| 24   x   x   x   x   x   x   x | 26       |       1      256       32       32 |       1      512       32       32 | 135266304 |
   27|TIDL_ConvolutionLayer         |conv5_6/dw                                        |     0|     1|     1| 25   x   x   x   x   x   x   x | 27       |       1      256       32       32 |       1      256       16       16 |    720896 |
   28|TIDL_ConvolutionLayer         |ctx_output1/sep/relu_mbox_loc_perm                |     0|     1|     1| 26   x   x   x   x   x   x   x | 28       |       1      512       32       32 |       1       16       32       32 |  75497472 |
   29|TIDL_ConvolutionLayer         |ctx_output2/dw                                    |     0|     1|     1| 25   x   x   x   x   x   x   x | 29       |       1      256       32       32 |       1      256       32       32 |   2883584 |
   30|TIDL_ConvolutionLayer         |ctx_output1/sep/relu_mbox_conf_perm               |     0|     1|     1| 26   x   x   x   x   x   x   x | 30       |       1      512       32       32 |       1        8       32       32 |  37748736 |
   31|TIDL_FlattenLayer             |ctx_output1/sep/relu_mbox_loc_flat                |     0|     1|     1| 28   x   x   x   x   x   x   x | 31       |       1       16       32       32 |       1        1        1    16384 |     16384 |
   32|TIDL_FlattenLayer             |ctx_output1/sep/relu_mbox_conf_flat               |     0|     1|     1| 30   x   x   x   x   x   x   x | 32       |       1        8       32       32 |       1        1        1     8192 |      8192 |
   33|TIDL_ConvolutionLayer         |conv5_6/sep                                       |     0|     1|     1| 27   x   x   x   x   x   x   x | 33       |       1      256       16       16 |       1      512       16       16 |  33816576 |
   34|TIDL_ConvolutionLayer         |ctx_output2/sep                                   |     0|     1|     1| 29   x   x   x   x   x   x   x | 34       |       1      256       32       32 |       1      512       32       32 | 135266304 |
   35|TIDL_ConvolutionLayer         |conv6/dw                                          |     0|     1|     1| 33   x   x   x   x   x   x   x | 35       |       1      512       16       16 |       1      512       16       16 |   1441792 |
   36|TIDL_ConvolutionLayer         |ctx_output2/sep/relu_mbox_loc_perm                |     0|     1|     1| 34   x   x   x   x   x   x   x | 36       |       1      512       32       32 |       1       16       32       32 |  75497472 |
   37|TIDL_ConvolutionLayer         |ctx_output3/dw                                    |     0|     1|     1| 33   x   x   x   x   x   x   x | 37       |       1      512       16       16 |       1      256       16       16 |   1310720 |
   38|TIDL_ConvolutionLayer         |ctx_output2/sep/relu_mbox_conf_perm               |     0|     1|     1| 34   x   x   x   x   x   x   x | 38       |       1      512       32       32 |       1        8       32       32 |  37748736 |
   39|TIDL_FlattenLayer             |ctx_output2/sep/relu_mbox_loc_flat                |     0|     1|     1| 36   x   x   x   x   x   x   x | 39       |       1       16       32       32 |       1        1        1    16384 |     16384 |
   40|TIDL_FlattenLayer             |ctx_output2/sep/relu_mbox_conf_flat               |     0|     1|     1| 38   x   x   x   x   x   x   x | 40       |       1        8       32       32 |       1        1        1     8192 |      8192 |
   41|TIDL_ConvolutionLayer         |conv6/sep                                         |     0|     1|     1| 35   x   x   x   x   x   x   x | 41       |       1      512       16       16 |       1      512       16       16 |  67371008 |
   42|TIDL_ConvolutionLayer         |ctx_output3/sep                                   |     0|     1|     1| 37   x   x   x   x   x   x   x | 42       |       1      256       16       16 |       1      512       16       16 |  33816576 |
   43|TIDL_PoolingLayer             |pool6                                             |     0|     1|     1| 41   x   x   x   x   x   x   x | 43       |       1      512       16       16 |       1      512        8        8 |    131072 |
   44|TIDL_ConvolutionLayer         |ctx_output3/sep/relu_mbox_loc_perm                |     0|     1|     1| 42   x   x   x   x   x   x   x | 44       |       1      512       16       16 |       1       16       16       16 |  18874368 |
   45|TIDL_ConvolutionLayer         |ctx_output4/dw                                    |     0|     1|     1| 41   x   x   x   x   x   x   x | 45       |       1      512       16       16 |       1      256       16       16 |   1310720 |
   46|TIDL_ConvolutionLayer         |ctx_output5/dw                                    |     0|     1|     1| 43   x   x   x   x   x   x   x | 46       |       1      512        8        8 |       1      256        8        8 |    327680 |
   47|TIDL_ConvolutionLayer         |ctx_output3/sep/relu_mbox_conf_perm               |     0|     1|     1| 42   x   x   x   x   x   x   x | 47       |       1      512       16       16 |       1        8       16       16 |   9437184 |
   48|TIDL_FlattenLayer             |ctx_output3/sep/relu_mbox_loc_flat                |     0|     1|     1| 44   x   x   x   x   x   x   x | 48       |       1       16       16       16 |       1        1        1     4096 |      4096 |
   49|TIDL_FlattenLayer             |ctx_output3/sep/relu_mbox_conf_flat               |     0|     1|     1| 47   x   x   x   x   x   x   x | 49       |       1        8       16       16 |       1        1        1     2048 |      2048 |
   50|TIDL_ConvolutionLayer         |ctx_output4/sep                                   |     0|     1|     1| 45   x   x   x   x   x   x   x | 50       |       1      256       16       16 |       1      512       16       16 |  33816576 |
   51|TIDL_ConvolutionLayer         |ctx_output5/sep                                   |     0|     1|     1| 46   x   x   x   x   x   x   x | 51       |       1      256        8        8 |       1      512        8        8 |   8454144 |
   52|TIDL_ConvolutionLayer         |ctx_output4/sep/relu_mbox_loc_perm                |     0|     1|     1| 50   x   x   x   x   x   x   x | 52       |       1      512       16       16 |       1       24       16       16 |  28311552 |
   53|TIDL_ConvolutionLayer         |ctx_output5/sep/relu_mbox_loc_perm                |     0|     1|     1| 51   x   x   x   x   x   x   x | 53       |       1      512        8        8 |       1       32        8        8 |   9437184 |
   54|TIDL_ConvolutionLayer         |ctx_output4/sep/relu_mbox_conf_perm               |     0|     1|     1| 50   x   x   x   x   x   x   x | 54       |       1      512       16       16 |       1       12       16       16 |  14155776 |
   55|TIDL_ConvolutionLayer         |ctx_output5/sep/relu_mbox_conf_perm               |     0|     1|     1| 51   x   x   x   x   x   x   x | 55       |       1      512        8        8 |       1       16        8        8 |   4718592 |
   56|TIDL_FlattenLayer             |ctx_output4/sep/relu_mbox_loc_flat                |     0|     1|     1| 52   x   x   x   x   x   x   x | 56       |       1       24       16       16 |       1        1        1     6144 |      6144 |
   57|TIDL_FlattenLayer             |ctx_output5/sep/relu_mbox_loc_flat                |     0|     1|     1| 53   x   x   x   x   x   x   x | 57       |       1       32        8        8 |       1        1        1     2048 |      2048 |
   58|TIDL_FlattenLayer             |ctx_output4/sep/relu_mbox_conf_flat               |     0|     1|     1| 54   x   x   x   x   x   x   x | 58       |       1       12       16       16 |       1        1        1     3072 |      3072 |
   59|TIDL_FlattenLayer             |ctx_output5/sep/relu_mbox_conf_flat               |     0|     1|     1| 55   x   x   x   x   x   x   x | 59       |       1       16        8        8 |       1        1        1     1024 |      1024 |
   60|TIDL_ConcatLayer              |mbox_loc                                          |     0|     5|     1| 31  39  48  56  57   x   x   x | 60       |       1        1        1    16384 |       1        1        1    45056 |     45056 |
   61|TIDL_ConcatLayer              |mbox_conf_flatten                                 |     0|     5|     1| 32  40  49  58  59   x   x   x | 61       |       1        1        1     8192 |       1        1        1    22528 |     22528 |
   62|TIDL_DetectionOutputLayer     |detection_out                                     |     0|     2|     1| 60  61   x   x   x   x   x   x | 62       |       1        1        1    45056 |       1        1        1     1404 |         0 |
   63|TIDL_DataLayer                |detection_out                                     |     0|     1|    -1| 62   x   x   x   x   x   x   x |  0       |       1        1        1     1404 |       0        0        0        0 |         0 |
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Total Giga Macs : 1.4725
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Observations:

a) Layer-0: It has no such pixels glitches

b) Layer-1 and Layer 2: It has a series of pixels glitches which is also found in the output image dumps of the model at Target side only.

Note: These glitches of pixels in the output are not observed on PC Emulation and Import side, it is present only at Target side.

Kindly help us to resolve the same.

Thanks and Regards,

Vyom Mishra

0 Vyom Mishra1 over 5 years ago in reply to Vyom Mishra1

Genius 4590 points

Dear Sir,

Gentle Reminder!

Thanks and Regards,

Vyom Mishra

0 Karthik Ramanan over 5 years ago

TI__Guru** 113810 points

We want to update this thread with some information. Subhajit will post further.

0 Subhajit Paul over 5 years ago in reply to Karthik Ramanan

TI__Expert 7015 points

Vyom Mishra,

I remember responding to this thread on 14th Jun, but I cannot see my response right now.

We have recently released a new SDK. Can you try to reproduce the issue on that?

- Subhajit

0 Subhajit Paul over 5 years ago in reply to Subhajit Paul

TI__Expert 7015 points

Closing this tread due to inactivity

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