CCS/TDA4VM: The cache coherence On TDA4

Tool/software: Code Composer Studio

In our algorithm, we will apply for two pieces of memory on L2, pSrcL2Blk and pDstL2Blk, to store input data and output data respectively.We first used UDMA(appUdmaCopy2D) to transfer the input data from DDR to pSrcL2Blk, and then C66 used the data on pSrcL2Blk for calculation, and then put the calculated results on pDstL2Blk, and finally used UDMA(appUdmaCopy2D) to transfer the data on pDstL2Blk to DDR. As shown in the following figure:

After UDMA has transferred data from pDstL2Blk to DDR, We used cache_wb to written back to DDR.

Our code is as follows:

Udma(pSrcL2Blk, pSrcDdr, srcWidth, srcHeight);

kernelProcess(pDstL2Blk, pSrcL2Blk);

        Udma(pDtsDdr, pDstL2Blk, dstWidth, dstHeight);

         Output_dim = dstWidth* dstHeight;

CacheP_wb(pDtsDdr, Output_dim);

We found the results incorrect, but we can be sure that the computational part of the kernelProcess is correct.

The specific parameters for the code in our project are: 

dstWidth = 288 dstHeight = 25 Output_dim =7200.