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TIDA-01573: How the power loop capacitance is estimated

Part Number: TIDA-01573

Hi:

     in the below equation(1) , how the 2V comes? isn't it 40V? 

2.2.1.2 Power Loop Capacitors
High-frequency capacitors for the power loop must provide currents in excess of 60 A with a rise time of ≈
300 ps (200 A/ns). The inductance of the loop is the main limiting element when dealing with those
speeds. The capacitors must be selected to allow for the maximum bus voltage. These capacitors must
provide both enough charge to sustain the current and a minimal inductive path.
X7R or better material is needed to provide stability and low ESR; a mix of 0603 and 0805 is necessary,
where the smaller capacitors are in the closest proximity to the power loop and the 0805 are adjacent to
those first capacitors. These materials are preferred if low-inductance, wide-body packages become
available.
The total value for the capacitance depends on the pulse repetition and pulse duration—in this case, a 1-
MHz repetition frequency for a 60-A, 1-ns pulse and a 40-V bus. To ensure the peak current is reached,
do not let the capacitor bank discharge more than 5% during the first half of the pulse.
     ( 60A x 1ns )/2V = 30-nF capacitance.           (1)

    

thanks

Zhang

  

    

  • Hi Zhang,

    Thanks for reaching out on tida-01573.

    This equation is derived from i = C dv/dt for the current sourced from a capacitor for a defined period of time with a known capacitor voltage with respect to time.

    The equation uses 2V and not 40V becuase, in the example for a 60A current pulse, we do not want the capacitor voltage to dip more than 5% of the 40V Vbus for a 1ns pulse. 5% of 40 is 2.

    If we choose the capacitor value of 30nF based on this we can verify that the capacitor voltage will not dip more than 2V when sourcing the 60A during the first half of the pulse when the peak current is reached.

    Let me know if this makes sense or you have any other questions.

    Thanks,

  • Hi Jeff:

       I now can understand why it's 2V instead of 40V.

         The 30nF can support a peak current of 60A with the bus voltage of 40V for 1ns period? I am a little doubtful about it.

         30nF capacitance is the minimum value required?

      Please check the schematic TIDA-01573.schdoc. 

       How is the total capacitance of  C2,C3,C6,C7,C8 and C9 calculated out? The total capacitance is 0.01+0.01+0.1+0.1+0.1+0.1=0.42uF.  

       is the total capacitance calculated out same as the equation for the 30nF?

     

       

    Thanks,

    Zhang

  • Hi Zhang,

    Thanks, that's correct the total output cap is calculated with this equation. However the pulse width value used is longer and less % of dip as well.

    Thanks,

  • Hi Jeff:

       Thank you for the help.

    thanks

    Zhang