Part Number: TLV9062
Tool/software: WEBENCH® Design Tools
Hi there,I have been checking the Linear Led driver from your reference design TIDA-010014 that uses the TLV9062 and a CSD17483F4 MOSFET
In the first AC Small Signal Stability Simulation you obtain a Phase Margin of 88.92 at a cross frequency of 3.95MEG using the following circuit
I understand the compensation network and the fact that L1 and C2 are there for DC and AC analysis and will act as a short or as an open circuit,however, I wonder why the designer used a DC voltage of 70mV (V2 in the image) injected into the non inverting input (+) of the OpAmp?For this kind of stability test we are supposed to tied to ground the non inverting input (+), am I right? adding this DC supply will change the behavior of the Open Loop Gain, 1/B and in general the Phase Margin of the circuit, and lead to a wrong stability analysis.
If we tied to ground the non inverting input (+) in the TINA SPICE file that you provided for this design we obtain totally different response with a very different Phase Margin for sure, as shown below:
In general, any other value smaller or larger than 70mV will completely change the response.
Am I getting lost somewhere ?
Any help will be appreciated.Thanks
First, recall that the transfer function of the circuit is Iout = Vin * R1, assuming the circuit has been properly designed. In this case, V2 = Vin.
If you remove VG2, remove C2, and replace L1 with a short, you can then run a DC sweep with V2 to find the DC operating region of the design. You will see that the response of the output current is linear for 0 < Vin < 100mV. So, the design has been made for input voltages of about 0 to 100mV. Below that, the amplifier essentially turns off and above that the output is saturated.
Now when you run a stability simulation, it is important that the amplifier is in the expected DC operating region. This will ensure that the amplifier is in its linear range. So, we want to ensure that Vin is in the region shown above. If you run an AC stability simulation where 0 < Vin < 100mV, you will see that the AolBeta response is essentially the same regardless of Vin. But outside of that region, you will get an unreasonable stability response. I would not tie V2 to 0V because this will try to take the inputs to 0V, which is the same as the V- rail voltage. Whenever you take the inputs to or beyond the supply rails, you won't get the linear op amp behavior.
One last thing to note: when you use this type of stability analysis, it is a good idea to model the input capacitance of the amplifier. This is explained in much more detail in this TI Precision Labs Video toward the end. Don't get confused by the different stability measurement response they are using. Just, look at the section explaining the input capacitance of the op amp.
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In reply to Daniel Miller56:
Thank you very much for your answer, I really appreciate it.
Also, thanks for pointing out the effect of the input capacitance inside the circuit for the open loop gain analysis. I did watch the video, it totally makes sense.
About the Open Loop Test, probably I got confused somewhere. In a PP presentation called Solving Op Amp Stability ( by Tim Green I think), he mention about Grounding Vin and even shows an example of a non inverting amplifier:
One last thing I would like to know about the reference design TIDA-010014 is about the Large Amplitude Transient Response, why do we apply 0V to the non inverting input of the Op Amp for this test?
Playing around with different values in the compensation network and Rsense ( for me to understand how the circuit works), for the same Large Amplitude Transient Response with an input voltage of 0V I obtain a response, with an Op Amp (VG) output long settling time like this one:Is it an indicator of instability? With a 5mv input it looks good without overshot, ringing or long settling times.
Thank you very much Daniel,Moises.
In reply to Moises Dominguez:
I'm happy that you found the video helpful. Grounding Vin typically works for a dual supply amplifier because it keeps both the inputs and output within the linear operating region of the amplifier. Here's the bottom line: when you run the stability test, you need to ensure that your DC biasing sets the amplifier in its linear operating region. It doesn't really matter where the bias point is as long as the amplifier is in that region. Usually what I will do is setup the circuit for the stability test, but first run a DC nodal analysis. If the inputs and output are well within the rails, then I am ok.
If you want to learn more about all this, I can point you to some more videos which cover the topic in detail.
Now I will answer your question about "why do we apply 0V to the non inverting input of the Op Amp for this test?" You actually do not. What happens is that the voltage shown in TINA is just the DC voltage set for the voltage source. However, when the transient analysis is run this DC voltage is not used. As you can see from the transient test, the voltage at Vin is not purely 0V but changes in time. So really, the voltage is not set at 0V for the test but is just shown that way in the schematic.
For your last question, would you mind sharing your schematic? I am not sure where VG is located. When it comes to measuring stability with a step voltage, we typically set the input voltage to get a 10mV step at the output. This presentation explains the process very well.
Let me know if you need further assistance.
Dear Daniel,Thank you so much for taking the time to answer and share your knowledge,About the presentation you linked, they do a Low Amplitude Transient Step simulation, and as you suggested, they looked for a 10mV step at the output. In the TIDA-010014 the also did it, but they separate the transient simulations in two parts:
1- Low amplitude step simulation where they looked for the 10mV output ( they use 1mV step with a DC level of 10mV).
2- Large Amplitude (high amplitude from zero) where they used a 150mV step with a DC level of 0) My last question was about the second part (high amplitude from zero) . Since I'm trying to really understand how the circuit works, I changed the compensation network and even used a different Op Amp (OPA365) with different characteristics too see how it affects the circuit, here is the schematic of the circuit I used with a 150mV step and a DC level of 0 (same as TIDA-010014). VG is the voltage at the gate of the MOSFET
The transient response is as follows:
OPA365 and CSD174 DC TEST.TSC
My question was about that strange settling time shown at VG, it indicates large signal stability issues ? Thank you again, it's been really nice learning from you,Moises.
For stability, we either look at the small signal response (overshoot with 10mV signal at output) or we perform the loop analysis in the AC domain.
Running a large signal test is good for measuring the slew rate response of the system. In your case, I think you see an RC response when there is a large signal step down because of C1. If you reduce the size of C1, you will see that the RC discharge effect is lessened.
Please let me know if you have any further questions or if I have misunderstood your question.
Dear Daniel,Thank you so much for your explanations,Yo have solved all my doubts.Just one little thing, I have been looking for this design notes everywhere on the TI website, and haven't succeed to find them. (The link does not work )https://e2e.ti.com/support/amplifiers/precision_amplifiers/w/design_notes/3600.high-current-v-i-circuits Is it possible that you can point me out where I can find them ?Thanks you,Best Regards,Moisés.
When the link redirects you to the FAQ page it means that the link is broken. I have tried looking for them on e2e and have not been successful. This leads me to believe that it has been removed.
All the best,Carolina
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