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Dear Team,
Would it be possible for you to explain about the working of power supply circuit. How input voltage is limited below 48V with 2 mosfets. very little is explained in the document.
I am not able to understand how N channel mosfet is reducing voltage.
It would be really helpful if you can share the detailed working or any reference?
Thanks and regards,
Monica
Hello
Let me contact the PDS engineer for this design and I will get back to you as soon as possible.
Thanks
Is Q21 the FET being discussed? If so, then the voltage at source pin3 is clamped by the gate voltage from VC5X_B, if the pin3 voltage is above the voltage from VC5X_B, the Q21 is turned off.